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| Number | Title | Issue Date |
| 6423632 | Semiconductor device and a process for forming the same A semiconductor device and a process for forming the device includes a conductor that overlies an insulating layer. In one embodiment, the conductor includes a first conductive portion, a second conductive portion, and a third conductive portion. The seco... | 07/23/2002 |
| 6420264 | Method of forming a silicide region in a Si substrate and a device having same A method of forming a silicide region (80) on a Si substrate (10) in the manufacturing of semiconductor integrated devices, a method of forming a semiconductor device (MISFET), and a device having suicide regions formed by the present method. The method o... | 07/16/2002 |
| 6420262 | Structures and methods to enhance copper metallization Structures and methods are described that inhibit atomic migration which otherwise creates an undesired capacitive-resistive effect arising from a relationship between a metallization layer and an insulator layer of a semiconductor structure. A layer of a... | 07/16/2002 |
| 6413859 | Method and structure for retarding high temperature agglomeration of silicides using alloys Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial... | 07/02/2002 |
| 6410429 | Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions A method for forming a void-free epitaxial cobalt silicide (CoSi2) layer on an ultra-shallow source/drain junction. A patterned silicon structure is cleaned using HF. A first titanium layer, a cobalt layer, and a second titanium layer are succe... | 06/25/2002 |
| 6410428 | Nitride deposition on tungsten-polycide gate to prevent abnormal tungsten silicide oxidation A method of forming a non-oxidized WSix layer on a semiconductor wafer, including the following steps. A semiconductor wafer having a silicon substrate is provided within a CVD tool. A WSix layer is formed over the silicon substrate.... | 06/25/2002 |
| 6410427 | Metal silicidation methods and methods for using same A method for use in the fabrication of semiconductor devices includes forming a layer of nitridated cobalt on a surface including silicon. A film cap including titanium is formed over the layer of cobalt and a thermal treatment is performed to form cobalt... | 06/25/2002 |
| 6410420 | Method of fabricating silicide pattern structures Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-co... | 06/25/2002 |
| 6406743 | Nickel-silicide formation by electroless Ni deposition on polysilicon The present invention provides a method of manufacturing a nickel-silicide technology for polysilicon interconnects. Nickel 40 is deposited on polysilicon 30 using a electroless process. Using a rapid thermal anneal process, Ni 40 is transformed to NiSi a... | 06/18/2002 |
| 6399485 | Semiconductor device with silicide layers and method of forming the same The present invention provides a semiconductor device having: at least a first diffusion layer having a first impurity concentration; at least a second diffusion layer having a first impurity concentration which is lower than the first impurity concentrat... | 06/04/2002 |
| 6399467 | Method of salicide formation A method of forming a self-aligned silicide (salicide) with a screening oxide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one... | 06/04/2002 |
| 6391767 | Dual silicide process to reduce gate resistance A method of reducing the gate resistance in a semiconductor device forms a gate in the semiconductor device followed by the creation of a silicide region on top of the gate. During the initial formation of the silicide region on the gate, formation of sil... | 05/21/2002 |
| 6387790 | Conversion of amorphous layer produced during IMP Ti deposition A method of fabricating a Ti-containing liner having good contact resistance and coverage of a contact hole is provided. The method which converts an amorphous region of ionized metal plasma deposited Ti into a substantially crystalline region includes (a... | 05/14/2002 |
| 6387789 | Method for fabricating semiconductor device Method for fabricating a semiconductor device, including the steps of (1) forming a gate insulating film, a silicon layer, and an insulating film on a substrate in succession, (2) selectively removing a portion of the insulating film on which a gate elect... | 05/14/2002 |
| 6383922 | Thermal stability improvement of CoSi2 film by stuffing in titanium A method for forming a thermally stable cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the silicon region... | 05/07/2002 |
| 6383905 | Formation of micro rough poly surface for low sheet resistance salicided sub-quarter micron poly lines This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide graiicide film during the f... | 05/07/2002 |
| 6383880 | NH3/N2-plasma treatment for reduced nickel silicide bridging Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a plasma containing ammonia and nitrogen... | 05/07/2002 |
| 6380063 | Raised wall isolation device with spacer isolated contacts and the method of so forming A semiconductor device having borderless contacts thereby providing a device having a reduced overall size. In particular, the device includes a plurality of shallow trench isolations and a plurality of dielectric isolations thereon to separate the adjoin... | 04/30/2002 |
| 6376358 | Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for t... | 04/23/2002 |
| 6372644 | Hydrogen passivated silicon nitride spacers for reduced nickel silicide bridging Bridging between nickel silicide layers on a gate electrode and associated source/drain regions along silicon nitride sidewall spacers is prevented by hydrogen passivation of the exposed surfaces of the silicon nitride sidewall spacers. Embodiments includ... | 04/16/2002 |
| 6372618 | Methods of forming semiconductor structures One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least... | 04/16/2002 |
| 6368963 | Passivation of semiconductor device surfaces using an iodine/ethanol solution Shorting between a transistor gate electrode and associated source/drain regions due to metal silicide formation on the sidewall spacers is prevented by passivating the sidewall spacer surfaces with a solution of iodine and ethanol. Embodiments of the inv... | 04/09/2002 |
| 6368960 | Double sidewall raised silicided source/drain CMOS transistor A method of forming a silicided device includes preparing a substrate by forming device areas thereon; providing structures that are located between the substrate and any silicide layers; forming a first layer of a first reactive material over the formed ... | 04/09/2002 |
| 6368950 | Silicide gate transistors A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal si... | 04/09/2002 |
| 6365511 | Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability The present invention provides a method of forming a metal stack structure over a substrate of a semiconductor device, comprising: (a) forming a first metal layer over the substrate, (b) forming a tungsten silicide nitride layer over the first metal layer... | 04/02/2002 |
| 6365497 | Method for making an I - shaped access transistor having a silicide envelop Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and cap... | 04/02/2002 |
| 6362095 | Nickel silicide stripping after nickel silicide formation A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; form... | 03/26/2002 |
| 6358846 | Method of fabricating semiconductor device with polycide gate structure A method of fabricating a semiconductor device is provided, which makes it possible to form a TiSi2 polycide gate structure having a crack-free TiSi2 film and which eliminates the process to lower the resistivity of a TiSi2 | 03/19/2002 |
| 6358844 | Tungsten deposition process with dual-step nucleation A tungsten plug deposition process that incorporates a dual-step nucleation method and the semiconductor structure formed by such method are disclosed. In the tungsten plug deposition process, a first nucleation layer is formed in the via openings in the ... | 03/19/2002 |
| 6350696 | Spacer etch method for semiconductor device Spacers are formed on a semiconductor device by depositing a spacer layer on the semiconductor device. The semiconductor device is subjected to an anisotropic etching process to leave at least a portion of the spacer layer covering the semiconductor devic... | 02/26/2002 |
| 6350684 | Graded/stepped silicide process to improve MOS transistor A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the inter... | 02/26/2002 |
| 6340629 | Method for forming gate electrodes of semiconductor device using a separated WN layer Disclosed is a method for forming gate electrodes using tungsten formed on a tungsten nitride layer by the chemical vapor deposition(CVD) process rather than the physical vapor deposition(PVD) process. According to the method for forming gate electrodes o... | 01/22/2002 |
| 6340620 | Method of fabricating a capacitor A process for fabricating a capacitor in a microcircuit, and the capacitor so fabricated. A first layer of a polycrystalline semiconductor, preferably polysilicon, is deposited. A layer of a binary metallic conductor, preferably tungsten silicide, is depo... | 01/22/2002 |
| 6339025 | Method of fabricating a copper capping layer A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the co... | 01/15/2002 |
| 6339021 | Methods for effective nickel silicide formation Methods for forming a high quality nickel silicide film in the fabrication of an integrated circuit are described. A semiconductor substrate is provided having silicon regions to be silicided wherein a native oxide layer forms on the silicon regions. A ni... | 01/15/2002 |
| 6337275 | Method for forming a self aligned contact in a semiconductor device A self aligned contact (SAC) pad in a semiconductor device and a method for forming thereof wherein an SAC opening is formed concurrently with single-layer gate spacers. After formation of the stacked gate pattern having a gate electrode and a capping lay... | 01/08/2002 |
| 6333262 | Method for forming silicide A method for forming silicide on a semiconductor wafer. The semiconductor wafer includes a doped silicon layer on a predetermined area of the semiconductor wafer, a metal layer positioned on the doped silicon layer, and a barrier layer covering the metal ... | 12/25/2001 |
| 6333259 | Semiconductor device and apparatus and method for manufacturing the same Disclosed is an apparatus for manufacturing a semiconductor device including a metal film which is formed on a semiconductor substrate in a film formation region containing the interior of a hole formed in the semiconductor substrate. The apparatus includ... | 12/25/2001 |
| 6333227 | Methods of forming hemispherical grain silicon electrodes by crystallizing the necks thereof The crystallinity of non-monocrystalline silicon necks that connect monocrystalline silicon hemispherical grains to an underlying electrode on an integrated circuit substrate is increased. Preferably, the non-monocrystalline silicon necks are crystallized... | 12/25/2001 |
| 6333222 | Semiconductor device and manufacturing method thereof In the method of manufacturing the DRAM mixed logic memory, first, a pattern of one gate electrode is formed, and then a pattern of another gate electrode is formed. A step of oxidizing a polycrystalline silicon residue is performed thereafter. Therefore,... | 12/25/2001 |
