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| Number | Title | Issue Date |
| 6969675 | Method of forming multilayer diffusion barrier for copper interconnections It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing... | 11/29/2005 |
| 6967134 | Methods of forming nitrogen-containing masses, silicon nitride layers, and capacitor constructions The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first ... | 11/22/2005 |
| 6967155 | Adhesion of copper and etch stop layer for copper alloy A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A ... | 11/22/2005 |
| 6967405 | Film for copper diffusion barrier The present invention provides a low dielectric constant copper diffusion barrier film suitable for use in a semiconductor device and methods for fabricating such a film. Some embodiments of the film are formed of a silicon-based material doped with boron. Other emb... | 11/22/2005 |
| 6962025 | Metal plasma surface-modified thermal barrier channel A method of modifying a thermal barrier assembly that includes a channel, the method including exposing a surface of a channel to a plasma that includes metal moieties and depositing the metal moieties on the surface of the channel. ... | 11/08/2005 |
| 6962873 | Nitridation of electrolessly deposited cobalt A method describing a low temperature process of forming a cobalt nitride layer using electroless deposition, followed by a nitridation step, is disclosed. The process described is useful in integrated circuit device fabrication applications, especially those involv... | 11/08/2005 |
| 6960524 | Method for production of a metallic or metal-containing layer The invention relates to a method for production of a metallic or metal-containing layer (5) by using a pre-cursor on a silicon- or germanium-containing layer, of, in particular, an electronic component, whereby an intermediate layer is applied to the silicon... | 11/01/2005 |
| 6960783 | Erasing and programming an organic memory device and method of fabricating An organic memory cell made of two electrodes with a selectively conductive media between the two electrodes is disclosed. The selectively conductive media contains an organic layer and passive layer. The selectively conductive media is programmed by applying bias v... | 11/01/2005 |
| 6958295 | Method for using a hard mask for critical dimension growth containment A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further include... | 10/25/2005 |
| 6958291 | Interconnect with composite barrier layers and method for fabricating the same Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, se... | 10/25/2005 |
| 6958290 | Method and apparatus for improving adhesion between layers in integrated devices In an integrated device, a via is formed in a substrate layer and a barrier layer is formed on the substrate layer in the via. A seed layer is formed on the barrier layer in the via. The seed layer includes a first material and a second material. The first material ... | 10/25/2005 |
| 6955962 | Deep trench capacitor having increased surface area A method of fabricating a trench capacitor of a memory cell, includes providing a semiconductor substrate with a surface covered by a pad layer, forming a trench in the substrate, forming a first layer on the pad layer and on the surface of the trench, removing a po... | 10/18/2005 |
| 6955983 | Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier ... | 10/18/2005 |
| 6955986 | Atomic layer deposition methods for forming a multi-layer adhesion-barrier layer for integrated circuits A process produces a layer of material which functions as a copper barrier layer, adhesion layer and a copper seed layer in a device of an integrated circuit, particularly in damascene or dual damascene structures. The method includes a step of depositing a diffusio... | 10/18/2005 |
| 6953749 | Methods of forming refractory metal silicide components and methods of restricting silicon surface migration of a silicon structure Methods of forming refractory metal suicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restric... | 10/11/2005 |
| 6953743 | Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is ... | 10/11/2005 |
| 6951809 | Method for manufacturing semiconductor device A lower barrier layer made of tantalum nitride having a thickness of approximately 25 nm is deposited by sputtering on a fourth insulating film inclusive of the sidewall surfaces and the bottom surfaces of a via hole and an upper-interconnect-forming groove. The spu... | 10/04/2005 |
| 6951804 | Formation of a tantalum-nitride layer A method of forming a tantalum-nitride layer (204) for integrated circuit fabrication is disclosed. Alternating or co-reacting pulses of a tantalum containing precursor and a nitrogen containing precursor are provided to a chamber (100) to form layers ... | 10/04/2005 |
| 6951786 | Method of forming a stack of refractory metal nitride over refractory metal silicide over silicon The invention encompasses methods of forming silicide interconnects over silicon comprising substrates. In one implementation, a first layer comprising a metal and a non-metal impurity is formed over a region of a silicon comprising substrate where a silicide interc... | 10/04/2005 |
| 6951814 | Methods for forming a metal wiring layer on an integrated circuit device at reduced temperatures Methods of forming a metal wiring layer on an integrated circuit include forming an insulating pattern including a recess region on an integrated circuit substrate. A metal layer is formed in the recess region and on a top surface of the insulting pattern. The metal... | 10/04/2005 |
| 6951813 | Methods of forming metal-containing layers including a metal bonded to halogens and trialkylaluminum The invention includes methods of forming metal-containing layers. The layers can, in particular aspects, consist essentially of metal, or consist of metal. The desired layers can be formed by initially depositing a metal-containing layer which comprises metal and h... | 10/04/2005 |
| 6949472 | Method for high kinetic energy plasma barrier deposition A novel method for depositing a barrier layer on a single damascene, dual damascene or other contact opening structure. The method eliminates the need for pre-cleaning argon ion bombardment of the structure, thereby reducing or eliminating damage to the surface of t... | 09/27/2005 |
| 6949471 | Method for fabricating poly patterns A method of fabricating polysilicon patterns. The method includes depositing polysilicon on a substrate. The polysilicon may be doped or pre-doped depending upon the application. A mask layer is applied and patterned. Thereafter, the polysilicon is etched to form th... | 09/27/2005 |
| 6949457 | Barrier enhancement A method of forming an electrically conductive via. A first electrically conductive layer is formed, and a second layer is formed on the first layer. The second layer has desired barrier layer properties. A third non electrically conductive layer is formed on the se... | 09/27/2005 |
| 6949786 | Semiconductor device including capacitor A semiconductor device is obtained that can prevent occurrence of a shape defect of a capacitor electrode in the semiconductor device or operation failure of the semiconductor device. A semiconductor device with the capacitor includes a second interlayer insulation ... | 09/27/2005 |
| 6949428 | Method for fabricating capacitor of semiconductor device In fabricating a capacitor of a semiconductor device, a first contact plug is formed in a plug contact hole formed by patterning a portion of a first interlayer insulating film formed on a substrate. A first barrier layer, a first polysilicon layer, and a second bar... | 09/27/2005 |
| 6946401 | Plasma treatment for copper oxide reduction The present invention provides an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion charac... | 09/20/2005 |
| 6946395 | Devices containing zirconium-platinum-containing materials and methods for preparing such materials and devices Methods for forming materials containing both zirconium and platinum, such as platinum-zirconium films, and articles containing such materials. The resultant films can be used as electrodes in an integrated circuit structure, particularly in a memory device such as ... | 09/20/2005 |
| 6943101 | Manufacturing of a corrosion protected interconnect on a substrate A method for fabricating an interconnect on a surface of a passivated substrate includes applying a diffusion barrier to the surface of the passivated substrate and applying a mask to the diffusion barrier. The mask is then patterned to provide an opening for the in... | 09/13/2005 |
| 6943076 | Semiconductor device and method of manufacturing the same Gate insulation films each containing titanium oxide as a primary constituent material are formed on one major surface of a semiconductor substrate. Gate electrode films are formed in contact with the gate insulation films. The gate electrode films contain ruthenium... | 09/13/2005 |
| 6943097 | Atomic layer deposition of metallic contacts, gates and diffusion barriers The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic sil... | 09/13/2005 |
| 6939800 | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on th... | 09/06/2005 |
| 6939797 | Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor depositio... | 09/06/2005 |
| 6939799 | Method of forming a field effect transistor and methods of forming integrated circuitry A method of forming integrated circuitry includes forming a field effect transistor gate over a substrate. The gate comprises polysilicon conductively doped with a conductivity enhancing impurity of a first type and a conductive diffusion barrier layer to diffusion ... | 09/06/2005 |
| 6939795 | Selective dry etching of tantalum and tantalum nitride The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which pass... | 09/06/2005 |
| 6940172 | Chemical vapor deposition of titanium A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second prec... | 09/06/2005 |
| 6936535 | Copper interconnect structure having stuffed diffusion barrier The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al int... | 08/30/2005 |
| 6936926 | Wiring structure in a semiconductor device A wiring structure includes a first wiring having a first wiring width, and a second wiring formed in the same layer as a layer in which the first wiring is formed, and having a second wiring width greater than the first wiring width. The second wiring is electrical... | 08/30/2005 |
| 6933549 | Barrier material A barrier layer protecting, for example, a ferroelectric capacitor from hydrogen is described. The barrier layer comprises aluminum oxide with barrier enhancement dopants. The barrier enhancement dopants are selected from Ti, Hf, Zr, their oxides, or a combination t... | 08/23/2005 |
| 6933021 | Method of TiSiN deposition using a chemical vapor deposition (CVD) process A method of forming a titanium silicide nitride (TiSiN) layer on a substrate id described. The titanium silicide nitride (TiSiN) layer is formed by providing a substrate to a process chamber and treating the substrate with a silicon-containing gas. A titanium nitrid... | 08/23/2005 |
