Class 438/649 - Silicide

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes for forming a conductive layer using the chemical
No. of patents: 596
Last issue date: 12/27/2011

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Number	Title	Issue Date
6277719	Method for fabricating a low resistance Poly-Si/metal gate A method for forming a low resistance metal/polysilicon gate for use in CMOS devices comprising: (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion barrier layer composed of titanium nitride deposited over ti...	08/21/2001
6274932	Semiconductor device having metal interconnection comprising metal silicide and four conductive layers A semiconductor device having a metal interconnection includes an insulating film provided on a semiconductor substrate via a diffusion layer. An interlayer contact hole is formed in the insulating film. A metal silicide layer is provided at the bottom of...	08/14/2001
6274517	Method of fabricating an improved spacer A method of fabricating an improved spacer comprising the steps of providing a semiconductor substrate that has a gate already formed thereon. A PNO spacer is formed on a sidewall of the gate. The method of forming the PNO spacer comprises first forming a...	08/14/2001
6271099	Method for forming a capacitor of a DRAM cell A method for forming a DRAM cell with a crown full metal capacitor electrode with integrated selective tungsten contact hole. When the MOSFET devices are defined, a metal landing pad with Ti/TiN/W/TiN is first deposited and etched. After an insulating lay...	08/07/2001
6271096	Method and device for improved salicide resistance on polysilicon gates A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a ...	08/07/2001
6268254	Method and device for improved salicide resistance on polysilicon gates A method and device for improved salicide resistance in polysilicon gates under 0.20 .mu.m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides ...	07/31/2001
6265291	Circuit fabrication method which optimizes source/drain contact resistance A method of manufacturing an integrated circuit to optimize the contact resistance between impurity diffusing layers and silicide is disclosed herein. The method includes implanting a first material to a layer of semiconductor to create a buried amorphous...	07/24/2001
6262485	Using implants to lower anneal temperatures A method for lowering the anneal temperature required to form a multi-component material, such as refractory metal silicide. A shallow layer of titanium is implanted in the bottom of the contact area after the contact area is defined. Titanium is then dep...	07/17/2001
6261940	Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containi...	07/17/2001
6258718	Method for reducing surface charge on semiconductor wafers to prevent arcing during plasma deposition A process of forming a layer of conductive material over a layer of insulating material is provided. A wafer is positioned on a wafer platform such that it is thermally and electrically coupled to the wafer platform. A clamping ring engages the peripheral...	07/10/2001
6258716	CVD titanium silicide for contact hole plugs A method of filling contact holes in a dielectric layer on an integrated circuit wafer. The method reduces processing steps and results in a reliable metal plug filling the contact hole. In one embodiment the contact hole is filled using blanket depositio...	07/10/2001
6258648	Selective salicide process by reformation of silicon nitride sidewall spacers A new method of forming selective salicide structures is described whereby robust salicide structures are formed on exposed logic FET's, while blocking salicide formation on memory FET's. Thus, yielding logic FET's with robust salicide structures which ex...	07/10/2001
6251777	Thermal annealing method for forming metal silicide layer A method for forming a metal silicide layer. There is first provided a substrate. There is then formed over the substrate a silicon layer, where the silicon layer has other than an amorphous silicon surface. There is then annealed thermally the silicon la...	06/26/2001
6245631	Method of forming buried bit line memory circuitry and semiconductor processing method of forming a conductive line The invention includes methods of forming buried bit line memory circuitry and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silic...	06/12/2001
6245673	Method of forming tungsten silicide film A first tungsten silicide layer relatively rich in silicon is formed on an object by using a process gas having a phosphorus atom-containing gas added thereto, and a second tungsten silicide layer relatively rich in tungsten is formed on the first tungste...	06/12/2001
6242348	Method for the formation of a boron-doped silicon gate layer underlying a cobalt silicide layer Process for forming a boron-doped silicon gate layer underlying a cobalt silicide layer that reduces the risk of grooving and agglomeration of cobalt silicide layer, as well as boron penetration into a gate oxide layer. The process includes providing a PM...	06/05/2001
6235566	Two-step silicidation process for fabricating a semiconductor device A two-step silicidation process for fabricating a semiconductor device is disclosed. The method includes the following steps. Firstly, two trench isolation regions are formed in a semiconductor substrate. A gate oxide layer and a polysilicon layer and a b...	05/22/2001
6235627	Semiconductor device and method for manufacturing the same A semiconductor device is formed by forming a groove portion whose side surface is formed of a first insulating film and whose bottom surface is formed of a silicon film on the main surface of a semiconductor substrate, forming a metal film on the silicon...	05/22/2001
6225155	Method of forming salicide in embedded dynamic random access memory In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain regio...	05/01/2001
6221764	Manufacturing method of semiconductor device After a cobalt film 12 and a titanium nitride film 13 as a barrier film against oxygen are formed over the surfaces of impurity diffusion layers 9, 10 on a silicon substrate 1, a first heat treatment is performed at a temperature below 400° C., forming a...	04/24/2001
6221792	Metal and metal silicide nitridization in a high density, low pressure plasma reactor A nitridization process to form a barrier layer on a substrate is described. The nitridization process includes depositing a layer of metal or metal silicide on a surface of the substrate, placing the substrate into a high density, low pressure plasma rea...	04/24/2001
6221762	Method for fabricating semiconductor device having improved step coverage and low resistivity contacts A method for fabricating a semiconductor device improves step coverage and resistivity. The method includes the steps of forming a doped silicon layer on a substrate, forming a silicide layer containing more metal atoms than silicon atoms on the doped sil...	04/24/2001
6214731	Copper metalization with improved electromigration resistance Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silan...	04/10/2001
6214713	Two step cap nitride deposition for forming gate electrodes A method for forming the gate electrode in an integrated circuit, in which a cap silicon nitride layer is deposited in a two step process to improve the condition of silicon nitride residue remaining on the surface of tungsten silicide. First, a layer of ...	04/10/2001
6214714	Method of titanium/titanium nitride integration A method of film processing comprises forming an integrated titanium/titanium nitride (Ti/TiN) film structure having an intermediate layer. The intermediate layer comprises species containing Si, and preferably containing Si and Ti, such as titanium silic...	04/10/2001
6211016	Method for forming high density nonvolatile memories with high capacitive-coupling ratio A method for fabricating a high speed and high density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the t...	04/03/2001
6211084	Method of forming reliable copper interconnects The adhesion of a diffusion barrier or capping layer to Cu and/or Cu alloy interconnect members is significantly enhanced by treating the exposed surface of the Cu and/or Cu alloy interconnect members with a silane or dichlorosilane plasma to form a layer...	04/03/2001
6211004	Semiconductor integrated circuit device and process for manufacturing the same A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting l...	04/03/2001
6204170	Method for manufacturing semiconductor device having metal silicide film and metal film in which metal film can be selectively removed In order to prevent a thick metal nitride film formed in a contact hole or a through-hole and on an insulating film to bury the hole from being cracked of peeled off, a method for easily removing unnecessary metal film on the insulating film while leaving...	03/20/2001
6200867	Method for forming raised source and drain A method for forming self-aligned raised source and drain regions on a semiconductor wafer includes the steps of defining a substrate, growing a first layer of dielectric material over the substrate, depositing a layer of polysilicon over the first layer ...	03/13/2001
6200910	Selective titanium nitride strip A strip for TiN with selectivity to TiSi2 consisting of a water solution of H2 O2 with possible small amounts of NH4 OH....	03/13/2001
6200895	Method of forming an electrical connection The present invention relates to high aspect-ratio electrical connections, wiring trenches, and methods of forming the same in semiconductor devices. In particular, the present invention relates to formation of contacts with refractory metal and/or refrac...	03/13/2001
6197629	Method of fabricating a polysilicon-based load circuit for static random-access memory A semiconductor fabrication method is provided for the fabrication of a polysilicon-based load circuit (called poly-load) for SRAM (static random-access memory). In accordance with this method, a lightly doped polysilicon layer is formed. This lightly dop...	03/06/2001
6194301	Method of fabricating an integrated circuit of logic and memory using damascene gate structure An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffus...	02/27/2001
6194315	Electrochemical cobalt silicide liner for metal contact fills and damascene processes A liner material and method of use is disclosed. The method includes depositing a silicon layer into a deep void, such as a via or trench, and physical vapor depositing a cobalt seed layer onto the silicon. A supplemental cobalt layer is electroplated ove...	02/27/2001
6190977	Method for forming MOSFET with an elevated source/drain A gate insulator layer is formed over the semiconductor substrate and a first silkcon layer is then formed over the gate insulator layer. An first dielectric layser is formed over the first silicon layer. A gate region is defined by removing a portion of ...	02/20/2001
6187625	Method of fabricating crown capacitor A method of fabricating a crown capacitor comprises first providing a substrate having a transistor, constituted by at least one diffused region, formed thereon and overlaid by a first insulating layer. Bit lines are formed in the first insulating layer. ...	02/13/2001
6187664	Method for forming a barrier metallization layer A method for forming a barrier metallization layer upon a semiconductor substrate. A semiconductor substrate is provided which has formed upon its surface a barrier metallization layer. The barrier metallization layer has formed in-situ upon its surface a...	02/13/2001
6187676	Integrated circuit insulated electrode forming methods using metal silicon nitride layers, and insulated electrodes so formed Insulated electrodes are formed by first forming on an integrated circuit substrate, an insulating layer, a conductive layer on the insulating layer, and a metal silicide layer on the conductive layer, and then forming a metal silicon nitride layer on the...	02/13/2001
6187665	Process for deuterium passivation and hot carrier immunity A process sequence for forming a semiconductor device utilizes a passivation annealing process using deuterium which enhances immunity to hot carrier effects and extends device lifetime. The process sequence is carried out prior to the introduction of met...	02/13/2001

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Class 438/649 - Silicide