Class 438/649 - Silicide

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes for forming a conductive layer using the chemical
No. of patents: 596
Last issue date: 12/27/2011

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Number	Title	Issue Date
8084359	Semiconductor package and methods of manufacturing the same A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive lay...	12/27/2011
8030210	Contact barrier structure and manufacturing methods A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal lay...	10/04/2011
8003526	Low resistance metal silicide local interconnects and a method of making A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The me...	08/23/2011
7858518	Method for forming a selective contact and local interconnect in situ A process for the in situ formation of a selective contact and a local interconnect on a semiconductor substrate. The exposed semiconductor substrate regions of a semiconductor device structure may be treated in a plasma to enhance the adhesiveness of a selective co...	12/28/2010
7816258	Method for manufacturing electro-optic device substrate with titanium silicide regions formed within An electro-optic device substrate includes a base and a TFT element having a source region and a drain region disposed on the base. The TFT element includes a silicon layer in the source region or the drain region, and the silicon layer at least partially includes a...	10/19/2010
7803706	Semiconductor device manufacturing method and semiconductor device Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transist...	09/28/2010
7732327	Vapor deposition of tungsten materials Embodiments of the invention provide an improved process for depositing tungsten-containing materials. The process utilizes soak processes and vapor deposition processes to provide tungsten films having significantly improved surface uniformity while increasing the ...	06/08/2010
7682968	Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structur...	03/23/2010
7638427	MOS transistor with fully silicided gate An MOS transistor with a fully silicided gate is produced by forming a silicide compound in the gate separately and independently of silicide portions located in source and drain zones of the transistor. To this end, the silicide portions of the source and drain zon...	12/29/2009
7605077	Dual metal integration scheme based on full silicidation of the gate electrode An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon...	10/20/2009
7432184	Integrated PVD system using designated PVD chambers A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one l...	10/07/2008
7425482	Non-volatile memory device and method for fabricating the same A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer c...	09/16/2008
7407882	Semiconductor component having a contact structure and method of manufacture A semiconductor component having a titanium silicide contact structure and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate. An opening having sidewalls is formed in the dielectric layer ...	08/05/2008
7405112	Low contact resistance CMOS circuits and methods for their fabrication A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first tra...	07/29/2008
7399701	Semiconductor device manufacturing method including forming a metal silicide layer on an indium-containing layer The present invention provides a semiconductor device manufacturing method of a semiconductor device having a contact plug, in which a contact hole formed by a surface portion of a high-concentration N-type diffusion layer formed on a semiconductor silicon substrate...	07/15/2008
7396764	Manufacturing method for forming all regions of the gate electrode silicided The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semico...	07/08/2008
7396724	Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer is protected from photoresist stripping chemicals by using a hard mask as a pattern during etching, rather than using a photoresist. The hard mask preve...	07/08/2008
7371333	Methods of etching nickel silicide and cobalt silicide and methods of forming conductive lines The invention includes methods of etching nickel silicide and cobalt silicide, and methods of forming conductive lines. In one implementation, a substrate comprising nickel silicide is exposed to a fluid comprising H3PO4 and H2O at a...	05/13/2008
7368392	Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ul...	05/06/2008
7364966	Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then f...	04/29/2008
7361597	Semiconductor device and method of fabricating the same A semiconductor device incorporating an alloy layer formed on a substrate; a gate electrode, a source electrode, and a drain electrode formed on the alloy layer at predetermined intervals therebetween; a gate insulating layer formed on the gate electrode in a gate e...	04/22/2008
7358143	Semiconductor device In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of...	04/15/2008
7358568	Low resistance semiconductor process and structures A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitri...	04/15/2008
7358188	Method of forming conductive metal silicides by reaction of metal with silicon The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a ni...	04/15/2008
7354838	Technique for forming a contact insulation layer with enhanced stress transfer efficiency By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may ...	04/08/2008
7349232	6FDRAM cell design with 3F-pitch folded digitline sense amplifier The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality o...	03/25/2008
7344984	Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwante...	03/18/2008
7344985	Nickel alloy silicide including indium and a method of manufacture therefor The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate ...	03/18/2008
7342286	Electrical node of transistor and method of forming the same According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage between the electrical node and a semiconductor substrate when a buried co...	03/11/2008
7338865	Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first tra...	03/04/2008
7338888	Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, ...	03/04/2008
7329604	Semiconductor device and method for fabricating the same The method for fabricating a semiconductor device comprises the step of forming a Co film 72 on a gate electrode 30 having a gate length Lg of below 50 nm including 50 nm; the first thermal processing step of making thermal processing to rea...	02/12/2008
7312140	Film forming method A technique is provided that is capable of employing raw materials having no halogen, which has a high possibility of exerting a bad influence upon semiconductor elements, thereby to easily form molybdenum films (molybdenum silicide films or molybdenum nitride films...	12/25/2007
7312150	Method of forming cobalt disilicide layer and method of manufacturing semiconductor device using the same A method of forming a cobalt disilicide layer and a method of manufacturing a semiconductor device using the same are provided. The method of forming a cobalt disilicide layer includes forming a cobalt layer on at least a silicon surface of a semiconductor device us...	12/25/2007
7312163	Atomic layer deposition methods, and methods of forming materials over semiconductor substrates The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least...	12/25/2007
7307017	Semiconductor devices and fabrication methods thereof Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device includes a silicon substrate, a source region and a drain region. A gate electrode is formed on the silicon substrate. Also, a metal silicide layer...	12/11/2007
7307871	SRAM cell design with high resistor CMOS gate structure for soft error rate improvement A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through ...	12/11/2007
7301190	Structures and methods to enhance copper metallization Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a meta...	11/27/2007
7291555	Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first material. The first and second materials are of different compositions, and are proximate one another at an in...	11/06/2007
7285467	Methods of fabricating static random access memories (SRAMS) having vertical transistors Unit cells of a static random access memory (SRAM) are provided including an integrated circuit substrate and first and second active regions. The first active region is provided on the integrated circuit substrate and has a first portion and a second portion. The s...	10/23/2007

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Class 438/649 - Silicide