Class 438/640 - Having viahole of tapered shape

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes wherein the viahole is formed so as to possess
No. of patents: 540
Last issue date: 05/01/2012

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Number	Title	Issue Date
8168531	Semiconductor device and method of fabricating the same A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate an...	05/01/2012
7892969	Method of manufacturing semiconductor device A method of manufacturing a semiconductor device has forming a first nitride layer over a substrate, forming a first oxide layer on the first nitride layer, forming a second nitride layer on the first oxide layer, forming a photoresist layer over the second nitride ...	02/22/2011
7879720	Methods of forming electrical interconnects using electroless plating techniques that inhibit void formation Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer....	02/01/2011
7838417	Semiconductor package with a chip on a support plate A semiconductor package includes a support plate made of an electrically non-conducting material. Electrical connection vias are formed outside a chip fixing region provided on the front face of the support plate. Electrical connection wires connect pads on a front ...	11/23/2010
7811931	Semiconductor device having a modified dielectric film A semiconductor device has a plurality of interconnect layers each including a plurality of interconnect lines. The semiconductor device includes a dielectric film (HDP film) formed by means of high density plasma-enhanced CVD and including an edge formed on the sid...	10/12/2010
7807567	Semiconductor device with interconnection structure for reducing stress migration The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug i...	10/05/2010
7772113	Post metal chemical mechanical polishing dry cleaning Metal residue on a semiconductor surface resulting from metal chemical mechanical polishing (“CMP”) process are eradicated using a dry clean process. The dry cleaning uniformly removes or substantially eliminates metal residue from the surface of the semiconduct...	08/10/2010
7670949	Semiconductor device and method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes: forming a first photosensitive material pattern having an opening hole on a work target layer formed on an active surface of a substrate; performing a first etching by performing an etching treatment to the ...	03/02/2010
7648910	Method of manufacturing opening and via opening A method of manufacturing an opening is described. First, a substrate including a conductive portion and a dielectric layer both formed thereon is provided. The conductive portion at least includes a conductive layer and a passivation layer from bottom-up, and the d...	01/19/2010
7648909	Method for fabricating semiconductor device with metal line A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a fi...	01/19/2010
RE40965	Method of forming low-resistance contact electrodes in semiconductor devices There is formed on a semiconductor substrate a lamination of a first insulating film of nondoped silicon glass or the like and, on this first insulating film, a second insulating film of boron phosphor silicate glass or the like, with a conductor layer between the t...	11/10/2009
7615486	Apparatus and method for integrated surface treatment and deposition for copper interconnect A method and system for depositing films on a substrate for copper interconnect in an integrated system are provided to enable controlled-ambient transitions within an integrated system to limit exposure of the substrate to uncontrolled ambient conditions. The metho...	11/10/2009
7598169	Method to remove beol sacrificial materials and chemical residues by irradiation A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remov...	10/06/2009
7569481	Method for forming via-hole in semiconductor device Disclosed is a method for forming a via-hole for interconnection of metallization and/or metal wires in a semiconductor device. The present method may include the steps of: (a) forming an insulating layer on a semiconductor substrate including a lower metallization ...	08/04/2009
7541282	Methods of forming metal-nitride layers in contact holes A metal layer can be formed in an integrated circuit by forming a metal-nitride layer in a recess including a first concentration of nitrogen in the metal-nitride layer at a bottom of the recess that is less than a second concentration of nitrogen in the metal-nitri...	06/02/2009
7524760	Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate, the interlayer dielectric layer h...	04/28/2009
7482267	Ion implantation of spin on glass materials A spin on glass SOG layer 30 is formed, then a PECVD barrier layer 40 over the SOG layer. Holes 50 in the SOG layer for vias are formed with a wine glass profile, so that in a peripheral region around the periphery of the holes, the barrier laye...	01/27/2009
7446036	Gap free anchored conductor and dielectric structure and method for fabrication thereof A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the fi...	11/04/2008
7422978	Methods of manufacturing interposers with flexible solder pad elements Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are formed from a core material of the interposer, such that the interposer...	09/09/2008
7416976	Method of forming contacts using auxiliary structures A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The pr...	08/26/2008
7410824	Method for solder bumping, and solder-bumping structures produced thereby A method for solder bumping provides a substrate and forms a film on the substrate. The film has openings therethrough. A stencil is aligned on the film. The stencil has openings therethrough over the openings through the film. Solder paste is printed onto the subst...	08/12/2008
7405156	Method of forming wiring pattern A photoresist pattern is formed on an insulating substrate so that it has a reverse tapered cross section and a reverse pattern of a wiring pattern to be formed. Next, a nanoparticles-containing ink is injected on a wiring region using an inkjet system, followed by ...	07/29/2008
7396762	Interconnect structures with linear repair layers and methods for forming such interconnection structures Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a condu...	07/08/2008
7388279	Tapered dielectric and conductor structures and applications thereof Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes ...	06/17/2008
7384866	Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier ...	06/10/2008
7361605	System and method for removal of photoresist and residues following contact etch with a stop layer present In processing an integrated circuit structure including a contact arrangement that is initially covered by a stop layer, a first plasma is used to etch to form openings through an overall insulation layer covered by a patterned layer of photoresist such that one con...	04/22/2008
7361588	Etch process for CD reduction of arc material A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can ...	04/22/2008
7358170	Methods of forming conductive interconnects, and methods of depositing nickel The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel sa...	04/15/2008
7354856	Method for forming dual damascene structures with tapered via portions and improved performance The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer...	04/08/2008
7341907	Single wafer thermal CVD processes for hemispherical grained silicon and nano-crystalline grain-sized polysilicon Methods for depositing hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are provided. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are deposited in single substrate chemical vapor ...	03/11/2008
7338897	Method of fabricating a semiconductor device having metal wiring A method of fabricating a semiconductor device includes forming a metal wire on a substrate, forming an interlayer insulating film on the metal wire, forming a resist pattern on the interlayer insulating film, selectively etching the interlayer film to form a trench...	03/04/2008
7335589	Method of forming contact via through multiple layers of dielectric material In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures a...	02/26/2008
7335517	Multichip semiconductor device, chip therefor and method of formation thereof A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the c...	02/26/2008
7329943	Microelectronic devices and methods for forming interconnects in microelectronic devices Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backs...	02/12/2008
7329601	Method of manufacturing semiconductor device Disclosed is a method for manufacturing a semiconductor device, comprising forming a low dielectric constant insulating film having a porous structure above a semiconductor substrate, forming a recess in the low dielectric constant insulating film, providing a buryi...	02/12/2008
7329956	Dual damascene cleaning method A semiconductor structure having a pore sealed portion of a dielectric layer is provided. Exposed pores of the dielectric material are sealed using an anisotropic plasma so that pores along the bottom of the opening are sealed, and pores along sidewalls of the openi...	02/12/2008
7326645	Methods for forming copper interconnect of semiconductor devices Methods for forming a copper interconnect of a semiconductor device are disclosed. A disclosed method comprises forming a lower metal interconnect; sequentially depositing a capping layer, a first insulating layer, and a second insulating layer on the lower metal in...	02/05/2008
7323409	Method for forming a void free via A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via...	01/29/2008
7319067	Method of simultaneously controlling ADI-AEI CD differences of openings having different sizes and etching process utilizing the same method A method of simultaneously controlling the ADI-AEI CD differences of openings having different sizes is disclosed. The openings are formed by: forming an ARC and a photoresist layer with a first and a second opening patterns of different sizes therein on a material ...	01/15/2008
7314828	Repairing method for low-k dielectric materials A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and per...	01/01/2008

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Class 438/640 - Having viahole of tapered shape