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| Number | Title | Issue Date |
| 6764941 | Bit line landing pad and borderless contact on bit line stud with localized etch stop layer and manufacturing method thereof An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as... | 07/20/2004 |
| 6764947 | Method for reducing gate line deformation and reducing gate line widths in semiconductor devices A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamina... | 07/20/2004 |
| 6753241 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or l... | 06/22/2004 |
| 6750137 | Method and apparatus for forming an interlayer insulating film and semiconductor device A method for forming an interlayer insulating film includes the steps of forming an underlying insulating film on a substrate; forming a film containing B (boron), C (carbon) and H2O) on the underlying insulating film by plasma enhanced chemical vapor dep... | 06/15/2004 |
| 6750085 | Method for manufacturing sidewall contacts for a chalcogenide memory device A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a sec... | 06/15/2004 |
| 6746954 | Method of reworking tungsten particle contaminated semiconductor wafers A method for reworking a metal particulate contaminated semiconductor wafer process surface following a metal dry etchback process including providing a semiconductor wafer including a dielectric insulating layer having anisotropically etched openings lined with a f... | 06/08/2004 |
| 6746945 | Method of forming a via hole in a semiconductor device A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF... | 06/08/2004 |
| 6740582 | Integrated circuits and methods for their fabrication To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed... | 05/25/2004 |
| 6737314 | Semiconductor device manufacturing method and semiconductor device A method for manufacturing a semiconductor device in which a MOS transistor having a reduction in a leakage current is obtained without unnecessarily damaging an integration of the transistor. After MOS transistor structures having a first sidewall are formed, an in... | 05/18/2004 |
| 6737349 | Method of forming a copper wiring in a semiconductor device A method of forming a copper wiring in a semiconductor device. The method can prevent an increase of a dielectric constant of a low dielectric constant film and making bad deposition of a copper anti-diffusion film, due to infiltration of an organic solvent, an etch... | 05/18/2004 |
| 6730570 | Method for forming a self-aligned contact of a semiconductor device and method for manufacturing a semiconductor device using the same A method for forming a self-aligned contact in a semiconductor device which can reduce process failures and a method for manufacturing a semiconductor device that includes the self-aligned contact are provided. A self-aligned contact hole is formed in an interlayer ... | 05/04/2004 |
| 6716769 | Use of a plasma source to form a layer during the formation of a semiconductor device A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further com... | 04/06/2004 |
| 6713388 | Method of fabricating a non-volatile memory device to eliminate charge loss A memory device is formed on a silicon substrate. A blocking layer is thereafter formed to cover a stacked gate of the memory device. A gettering layer is formed on the blocking layer followed by planarizing of the gettering layer to a predetermined thickness. A fir... | 03/30/2004 |
| 6713386 | Method of preventing resist poisoning in dual damascene structures A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed o... | 03/30/2004 |
| 6713337 | Method for manufacturing a semiconductor device having self-aligned contacts A semiconductor device comprises an SAC structure having side wall spacers and offset nitride films. In particular, in this semiconductor device, the side wall spacers are constituted from lower side wall spacers that are composed of silicon oxide films and are in c... | 03/30/2004 |
| 6709975 | Method of forming inter-metal dielectric A method of forming inter-metal dielectric (IMD). A substrate having a patterned metal layer thereon has at least one opening to expose the substrate. The opening has an aspect ratio of 3.5˜4.5. Next, the opening is filled with a first dielectric layer, and voids a... | 03/23/2004 |
| 6703310 | Semiconductor device and method of production of same A semiconductor device, enabling reliable electrical connection of a main electrode pad with an interconnection pattern without separate provision of a via use electrode pad in addition to the existing main electrode pad, provided with a silicon substrate... | 03/09/2004 |
| 6703308 | Method of inserting alloy elements to reduce copper diffusion and bulk diffusion A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a seco... | 03/09/2004 |
| 6699785 | Conductor abrasiveless chemical-mechanical polishing in integrated circuit interconnects A manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A... | 03/02/2004 |
| 6696368 | Titanium boronitride layer for high aspect ratio semiconductor devices Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The contacts are useful for providing electrical connection to active components beneath an insulation layer in integrated circuits such as m... | 02/24/2004 |
| 6696339 | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices The present invention is directed toward methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices. For example, one embodiment is directed tow... | 02/24/2004 |
| 6689684 | Cu damascene interconnections using barrier/capping layer Interconnects to an underlying Cu feature are formed with improved reliability by replacing a portion of the capping layer in the bottom of an opening in an overlying dielectric layer, e.g., an ILD, with a barrier material, such as Ta or TaN. During Ar sp... | 02/10/2004 |
| 6683002 | Method to create a copper diffusion deterrent interface Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.... | 01/27/2004 |
| 6682999 | Semiconductor device having multilevel interconnections and method of manufacture thereof The present invention provides, in one aspect, a method for fabricating an interconnect system within a semiconductor device. In this particular embodiment, the method comprises forming a conductive layer over a substrate of the semiconductor device, such... | 01/27/2004 |
| 6680247 | Manufacturing method of a semiconductor device The manufacturing method of a semiconductor device includes a step of forming a lower wiring on a semiconductor substrate, a step of forming a layer insulating film on the lower wiring, a step of forming an opening that exposes the lower wiring by removin... | 01/20/2004 |
| 6667551 | Semiconductor device and manufacturing thereof, including a through-hole with a wider intermediate cavity A method of manufacturing a semiconductor device comprises a step of forming a through-hole in a semiconductor chip having an electrode and forming a conductive layer on a region comprising an inner side of the through-hole. An intermediate portion of the... | 12/23/2003 |
| 6667236 | Method of manufacturing a two layer liner for dual damascene vias The invention relates to a semiconductor device comprising a substrate (1) comprising for instance silicon with thereon a layer (2, 4) comprising at least organic material which contains a passage (6, 8) to the substrate (1). The passage (6,8) has walls (... | 12/23/2003 |
| 6653737 | Interconnection structure and method for fabricating same An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s).... | 11/25/2003 |
| 6653228 | Method for preparing semiconductor including formation of contact hole using difluoromethane gas A method for forming a contact hole in a semiconductor device includes the steps of forming a polymer layer on an upper portion and a side wall of photo resist mask, while etching an oxide layer under the photoresist mask to form a contact hole that uses ... | 11/25/2003 |
| 6649515 | Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures A method of forming an interconnection including the steps of depositing a first masking material over a first conductive region of an integrated circuit substrate and depositing a dielectric material over the first masking material. The method also inclu... | 11/18/2003 |
| 6649503 | Methods of fabricating integrated circuit devices having spin on glass (SOG) insulating layers and integrated circuit devices fabricated thereby Methods are provided for forming integrated circuit devices. A spin on glass (SOG) insulating layer is formed on an integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are formed on the s... | 11/18/2003 |
| 6642145 | Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-ba... | 11/04/2003 |
| 6642144 | Method of forming memory device having capacitor including layer of high dielectric constant A method of fabricating a semiconductor device having a capacitor with a high dielectric constant layer includes a groove for an alignment key is formed together with a contact hole on a substrate; a conductive layer of tungsten is formed to fill the cont... | 11/04/2003 |
| 6638805 | Method of fabricating a DRAM semiconductor device A method of fabricating a DRAM semiconductor device including forming gate stacks in which a gate pattern and a gate sacrificial mask are sequentially deposited on a semiconductor substrate, forming an etch stopper on the semiconductor substrate, forming ... | 10/28/2003 |
| 6627493 | Self-aligned method for fabricating a capacitor under bit-line (cub) dynamic random access memory (DRAM) cell structure Within a method for fabricating a dynamic random access memory (DRAM) cell structure there is first anisotropically sequentially etched a blanket hard mask layer and a blanket capacitor plate layer which both cover a bit-line source/drain region within th... | 09/30/2003 |
| 6624065 | Method of fabricating a semiconductor device using a damascene metal gate A method of fabricating a semiconductor device using a damascene metal gate including the steps of forming a damascene gate oxide layer and a damascene gate electrode on a semiconductor substrate, forming a trench at an upper part of the damascene gate el... | 09/23/2003 |
| 6617232 | Method of forming wiring using a dual damascene process A method of forming electric wiring using a dual damascene process wherein prevention of damage to a lower conductive pattern and low contact resistance may be achieved. A first insulation layer having a first trench filled with a conductive material is f... | 09/09/2003 |
| 6613668 | Two layer liner for dual damascene via The invention relates to a semiconductor device having a substrate (1) for instance silicon, with a layer (2, 4) of at least organic material which contains a passage (6, 8) to the substrate (1). The passage (6,8) has walls (7, 9) transverse to the layer ... | 09/02/2003 |
| 6602780 | Method for protecting sidewalls of etched openings to prevent via poisoning A method for forming a protective oxide liner to reduce a surface reflectance including providing a hydrophilic insulating layer over a conductive layer; providing an anti-reflectance coating (ARC) layer over the hydrophilic insulating layer; providing an... | 08/05/2003 |
| 6602788 | Process for fabricating an interconnect for contact holes A process for fabricating an interconnect for contact holes includes forming contact holes in an insulation layer leading to a first interconnect layer, cleaning the hole surface, forming a barrier layer on the hole surface, forming an AlGeCu-containing s... | 08/05/2003 |
