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| Number | Title | Issue Date |
| 7371677 | Laterally grown nanotubes and method of formation A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portio... | 05/13/2008 |
| 7365001 | Interconnect structures and methods of making thereof A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in ... | 04/29/2008 |
| 7365408 | Structure for photolithographic applications using a multi-layer anti-reflection coating A bi-layer anti-reflective coating for use in photolithographic applications, and specifically, for use in ultraviolet photolithographic processes. The bi-layered anti-reflective coating is used to minimize pattern distortion due to reflections from neighboring feat... | 04/29/2008 |
| 7363694 | Method of testing using compliant contact structures, contactor cards and test system A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the sub... | 04/29/2008 |
| 7361589 | Copper interconnect systems which use conductive, metal-based cap layers An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 04/22/2008 |
| 7361605 | System and method for removal of photoresist and residues following contact etch with a stop layer present In processing an integrated circuit structure including a contact arrangement that is initially covered by a stop layer, a first plasma is used to etch to form openings through an overall insulation layer covered by a patterned layer of photoresist such that one con... | 04/22/2008 |
| 7358568 | Low resistance semiconductor process and structures A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitri... | 04/15/2008 |
| 7358597 | UV-activated dielectric layer A dielectric layer on a semiconductor substrate is made porous by radiation with UV light. The dielectric material contains a photosensitive moiety that absorbs UV radiation and dissociates from the dielectric material. The UV-activated material then may be diffused... | 04/15/2008 |
| 7358170 | Methods of forming conductive interconnects, and methods of depositing nickel The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel sa... | 04/15/2008 |
| 7352064 | Multiple layer resist scheme implementing etch recipe particular to each layer Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first plan... | 04/01/2008 |
| 7344976 | Method for fabricating nonvolatile semiconductor memory device An adhesion layer composed of a titanium film and a titanium nitride film is formed by CVD on the inner wall of a contact hole formed in a multilayer film composed of an interlayer insulating film, a silicon nitride film, and a silicon dioxide film. Then, a conducti... | 03/18/2008 |
| 7344974 | Metallization method of semiconductor device A method for forming a metallization contact in a semiconductor device includes the steps of: (a) forming an insulating layer on a semiconductor substrate including an active device region; (b) forming a contact hole to expose a portion of the active device region b... | 03/18/2008 |
| 7342301 | Connection device with actuating element for changing a conductive state of a via A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of t... | 03/11/2008 |
| 7341936 | Semiconductor device and method of manufacturing the same A semiconductor device manufacturing method comprises the steps of forming a metal film (24) on an organic interlayer insulating film (22) formed over a semiconductor substrate to get a metal diffusion preventing metal carbide film (23) on a bou... | 03/11/2008 |
| 7338871 | Method for fabricating semiconductor device The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conduc... | 03/04/2008 |
| 7338895 | Method for dual damascene integration of ultra low dielectric constant porous materials A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k ... | 03/04/2008 |
| 7335981 | Methods for creating electrophoretically insulated vias in semiconductive substrates Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the l... | 02/26/2008 |
| 7335517 | Multichip semiconductor device, chip therefor and method of formation thereof A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the c... | 02/26/2008 |
| 7335589 | Method of forming contact via through multiple layers of dielectric material In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures a... | 02/26/2008 |
| 7335592 | Wafer level package, multi-package stack, and method of manufacturing the same A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of t... | 02/26/2008 |
| 7332428 | Metal interconnect structure and method In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via is formed within the dielectric layer. A liner is formed over the dual damascene structure. The liner is... | 02/19/2008 |
| 7329601 | Method of manufacturing semiconductor device Disclosed is a method for manufacturing a semiconductor device, comprising forming a low dielectric constant insulating film having a porous structure above a semiconductor substrate, forming a recess in the low dielectric constant insulating film, providing a buryi... | 02/12/2008 |
| 7329602 | Wiring structure for integrated circuit with reduced intralevel capacitance A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated fr... | 02/12/2008 |
| 7326647 | Dry etching process to form a conductive layer within an opening without use of a mask during the formation of a semiconductor device A method for use in fabrication of a semiconductor device comprises forming a conformal conductive layer over a planarized surface of a dielectric layer, and within an opening formed in the dielectric layer. The opening will typically have an aspect ratio of about 4... | 02/05/2008 |
| 7326645 | Methods for forming copper interconnect of semiconductor devices Methods for forming a copper interconnect of a semiconductor device are disclosed. A disclosed method comprises forming a lower metal interconnect; sequentially depositing a capping layer, a first insulating layer, and a second insulating layer on the lower metal in... | 02/05/2008 |
| 7323410 | Dry etchback of interconnect contacts A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tu... | 01/29/2008 |
| 7319274 | Methods for selective integration of airgaps and devices made by such methods Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer incl... | 01/15/2008 |
| 7316974 | Wiring pattern formation method, manufacturing method for multi layer wiring substrate, and electronic device A wiring pattern formation method in which a wiring pattern is formed by arranging, in a region which is demarcated by a partition wall, liquid material which includes an electrically conductive material, including: arranging a resin material around the periphery of... | 01/08/2008 |
| 7317253 | Cobalt tungsten phosphate used to fill voids arising in a copper metallization process A semiconductor device includes a substrate, at least one layer of functional devices formed on the substrate, a first dielectric layer formed over the functional device layer and a first trench/via located in the first dielectric layer. A copper conductor fills the... | 01/08/2008 |
| 7312121 | Method of manufacturing a semiconductor memory device Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer co... | 12/25/2007 |
| 7312400 | Multilayer wiring board, base for multilayer wiring board, printed wiring board and its manufacturing method A multilayer wiring board assembly component comprises: an insulating substrate component (the insulating resin layer 111); a conductive layer 112 formed on one surface of said insulating substrate component 111 in the form of an electrode patte... | 12/25/2007 |
| 7309639 | Method of forming a metal trace with reduced RF impedance resulting from the skin effect The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an inc... | 12/18/2007 |
| 7309649 | Method of forming closed air gap interconnects and structures formed thereby A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remai... | 12/18/2007 |
| 7303965 | MIS transistor and method for producing same In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain re... | 12/04/2007 |
| 7301190 | Structures and methods to enhance copper metallization Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a meta... | 11/27/2007 |
| 7300868 | Damascene interconnection having porous low k layer with a hard mask reduced in thickness A method is provided of fabricating a damascene interconnection. The method begins by forming on a substrate a first dielectric layer, a capping layer on the first dielectric sublayer and a resist pattern over the capping layer to define a first interconnect opening... | 11/27/2007 |
| 7297628 | Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etch Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielec... | 11/20/2007 |
| 7285196 | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requir... | 10/23/2007 |
| 7282412 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/16/2007 |
| 7282437 | Insulating tube, semiconductor device employing the tube, and method of manufacturing the same An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as ... | 10/16/2007 |
