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| Number | Title | Issue Date |
| 6475905 | Optimization of organic bottom anti-reflective coating (BARC) thickness for dual damascene process A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the fir... | 11/05/2002 |
| 6475891 | Method of forming a pattern for a semiconductor device A method of forming a pattern for a semiconductor device without using a photolithography technique is disclosed, wherein the method includes forming a sacrificial layer on a semiconductor substrate, forming a sacrificial layer pattern by patterning the s... | 11/05/2002 |
| 6472307 | Methods for improved encapsulation of thick metal features in integrated circuit fabrication The present invention provides a method of manufacturing an integrated circuit having a capping layer over a thick metal feature. In one embodiment, the method comprises forming first and second oxide layers over the thick metal feature, forming a composi... | 10/29/2002 |
| 6458692 | Method of forming contact plug of semiconductor device A method of forming contact plugs of a semiconductor device is provided. Bit lines are formed over a semiconductor substrate in which a predetermined lower layer is formed and a cell area and a core area are defined. An interlayer dielectric layer is form... | 10/01/2002 |
| 6444575 | Method for forming a bitline contact via within a memory cell structure Within a method for forming a contact via there is provided a substrate having formed thereover a pair of topographic structures separated by a contact region formed within the substrate. There is then formed upon the substrate and the pair of topographic... | 09/03/2002 |
| 6440846 | Method for forming semiconductor device In a method for forming a semiconductor device, when polishing the wafer, the photo-resin so as to cure with ultraviolet is buried. Then, after polishing and forming the back side electrode, the photo-resin is removed by organic solvent. Accordingly, the ... | 08/27/2002 |
| 6440847 | Method for forming a via and interconnect in dual damascene A first low-k layer is formed over a structure having an exposed active device. A patterned first nitride layer having an opening therethrough aligned over a portion of the active device is formed. Nitride spacers are formed over the side walls of the ope... | 08/27/2002 |
| 6440850 | Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and impro... | 08/27/2002 |
| 6436814 | Interconnection structure and method for fabricating same An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s).... | 08/20/2002 |
| 6429123 | Method of manufacturing buried metal lines having ultra fine features The present invention provides a method for manufacturing a plurality of buried metal lines on a semiconductor substrate. The method comprises the steps as below. A dielectric layer is formed on a semiconductor substrate. And a plurality of insulator bloc... | 08/06/2002 |
| 6426293 | Minimizing resistance and electromigration of interconnect by adjusting anneal temperature and amount of seed layer dopant A plurality of test interconnect structures are formed with each test interconnect structure having a respective alloy seed layer and with a fill conductive material formed to fill the respective interconnect opening. The respective alloy seed layer of ea... | 07/30/2002 |
| 6417094 | Dual-damascene interconnect structures and methods of fabricating same An interconnect fabrication process and structure provides barrier enhancement at the via sidewalls and improved capability to fabricate high aspect ratio dual damascene interconnects. A via structure is patterned into the via dielectric first, then a die... | 07/09/2002 |
| 6410423 | Semiconductor device and manufacturing method thereof A semiconductor device comprises a first insulating film formed over a semiconductor substrate, a second insulating film formed on the first insulating film, a contact plug made of a conductive material vertically penetrating the first and second insulati... | 06/25/2002 |
| 6406993 | Method of defining small openings in dielectric layers The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an o... | 06/18/2002 |
| 6399480 | Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming loca... | 06/04/2002 |
| 6395631 | Low dielectric constant dielectric layer fabrication method employing hard mask layer delamination A method for forming, within a low dielectric constant dielectric layer formed upon a substrate employed within a microelectronics fabrication, a conductor pattern employing a hard mask cap layer. There is first provided a substrate having conductor regio... | 05/28/2002 |
| 6391761 | Method to form dual damascene structures using a linear passivation A method to form dual damascene structures is described. A substrate layer is provided. An anti-diffusion layer is deposited. A first dielectric layer is deposited. An etch stopping layer is deposited. A second dielectric layer is deposited. The second di... | 05/21/2002 |
| 6383920 | Process of enclosing via for improved reliability in dual damascene interconnects The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched an... | 05/07/2002 |
| 6383911 | Semiconductor device and method for making the same A semiconductor device having: a first interconnect or electrode formed on a substrate; an organic insulation film which is formed covering the first interconnect or electrode and in which an interconnect trench and an interlayer connection hole reaching ... | 05/07/2002 |
| 6383862 | Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole A method of forming a contact hole in a semiconductor device is provided wherein an oxide spacer is formed over a contact hole. The oxide contact hole spacer prevents an already-formed gate protecting spacer comprised of silicon nitride from being etched ... | 05/07/2002 |
| 6380003 | Damascene anti-fuse with slot via Interconnect structures comprising a substrate having a first level of electrically conductive features formed thereon; a patterned interlevel dielectric material formed on said substrate, wherein said patterned interlevel dielectric includes via spaces, ... | 04/30/2002 |
| 6380065 | Interconnection structure and fabrication process therefor In a related interconnection structure that is formed by filling a metal, there have been problems, since defective connection occurs due to generation of voids and other features caused by poor filling of the metal, which entails reduction in reliability... | 04/30/2002 |
| 6376356 | Method of manufacturing a metal wiring in a semiconductor device A method of manufacturing a metal wiring in a semiconductor device is disclosed. The method comprises forming a photosensitive film so that an underlying metal wiring can be exposed, adhering an chemical enhancer only to the underlying metal wiring, depos... | 04/23/2002 |
| 6376386 | Method of etching silicon nitride by a mixture of CH2 F2, CH3F or CHF3 and an inert gas There are included steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer, loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere, and selectively etching the silicon ni... | 04/23/2002 |
| 6376368 | Method of forming contact structure in a semiconductor device A method of forming a contact structure in a semiconductor device is provided. In this method, a semiconductor layer, an ohmic metal layer, and a barrier metal layer are formed on the surface of a semiconductor substrate on which a metal contact hole has ... | 04/23/2002 |
| 6376298 | Layout method for scalable design of the aggressive RAM cells using a poly-cap mask A method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits by using a poly cap mask and a special layout technique is described. A pair of gate electrodes and associated source and drain regions are form... | 04/23/2002 |
| 6372636 | Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure -single, dual, or multi-structure- is disclosed in order to prevent the formation of fluorides in copper. In a first em... | 04/16/2002 |
| 6372575 | Method for fabricating capacitor of dram using self-aligned contact etching technology The present invention discloses a method for fabricating a capacitor of a semiconductor device. In the conventional art, a bit line may be shifted or bent differently from the definition on a mask due to the stress resulting from a material difference bet... | 04/16/2002 |
| 6365504 | Self aligned dual damascene method A method for fabricating an interconnection between a conductive line and a via plug on an insulating layer, comprises the steps of: forming a conductive line pattern on the insulating layer; etching the upper part of the insulating layer and forming a co... | 04/02/2002 |
| 6365513 | Method of making a semiconductor device including testing before thinning the semiconductor substrate A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in ... | 04/02/2002 |
| 6362083 | Method for fabricating locally reinforced metallic microfeature A method for fabricating a locally reinforced metallic microfeature on a substrate provided preferably with an electrical contacting or a driving circuit, and on an organic, patterned sacrificial layer, which is removed after the metallic microfeature is ... | 03/26/2002 |
| 6358800 | Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit A method of forming a MOSFET having a recessed-gate with a channel length beyond the photolithography limit is disclosed in the present invention. First, a first dielectric layer and a second dielectric layer are formed on a semiconductor substrate. A fir... | 03/19/2002 |
| 6355549 | Method of forming polycide structures A method of forming a polycide structure in accordance with the present invention includes forming a polysilicon layer on a surface. A refractory metal silicide portion of the polycide structure is formed on the polysilicon layer and the polysilicon porti... | 03/12/2002 |
| 6352913 | Damascene process for MOSFET fabrication An improved MOSFET transistor is disclosed having a high dielectric constant gate dielectric and a metal gate electrode. With such a procedure, the known problems with polysilicon gate electrodes on very thin gate oxide transistors are greatly improved, r... | 03/05/2002 |
| 6352917 | Reversed damascene process for multiple level metal interconnects A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is pr... | 03/05/2002 |
| 6344391 | Fabrication method of semiconductor device with diagonal capacitor bit line A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a... | 02/05/2002 |
| 6337266 | Small electrode for chalcogenide memories A method for fabricating an ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally, in which disposable spacers are utilized to fabricate ultra-small pores into which the electrodes ... | 01/08/2002 |
| 6337267 | Method for fabricating a semiconductor memory device and the structure thereof A method for fabricating a semiconductor device, wherein a dual damascene metal line is formed utilising a material layer pattern. The material layer pattern has openings to define contact holes both for metal interconnection in the peripheral region and ... | 01/08/2002 |
| 6335275 | Method for forming contact holes and semiconductor device fabricated using the same An insulating layer and a first silicon system layer are formed on a semiconductor substrate. An opening is formed in the first silicon system layer. A second silicon system layer is provided to cover the first silicon system layer and the opening. The se... | 01/01/2002 |
| 6329255 | Method of making self-aligned bit-lines The present invention provides a method of making self-aligned bit-lines on a substrate, the surface of which comprises a dielectric layer having a plurality of node contact holes and bit-line contact holes. A first conducting layer is formed on the surfa... | 12/11/2001 |
