Class 438/639 - Having viahole with sidewall component

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes wherein the viahole has an additional component
No. of patents: 762
Last issue date: 05/15/2012

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Number	Title	Issue Date
8178440	Method for forming a recess array device structure in a semiconductor substrate The present invention relates to a method for forming a recess array device structure in a semiconductor substrate. The method includes the steps of: providing a base material including a semiconductor substrate and a first material; forming a plurality of second re...	05/15/2012
8097536	Reducing metal voids in a metallization layer stack of a semiconductor device by providing a dielectric barrier layer Metallization systems on the basis of copper and low-k dielectric materials may be efficiently formed by providing an additional dielectric material of enhanced surface conditions after the patterning of the low-k dielectric material. Consequently, defects such as i...	01/17/2012
8053360	Semiconductor device and method of manufacturing the same To prevent two contacts that have different heights, share at least one interlayer insulating film and are disposed close to each other from being short-circuited to each other due to misalignment thereof, a semiconductor device according to the invention has a rece...	11/08/2011
8048798	Method for manufacturing a nonvolatile semiconductor storage device where memory cells are arranged three dimensionally A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and...	11/01/2011
8026173	Semiconductor structure, in particular phase change memory device having a uniform height heater A phase change memory formed by a plurality of phase change memory devices having a chalcogenide memory region extending over an own heater. The heaters have all a relatively uniform height. The height uniformity is achieved by forming the heaters within pores in an...	09/27/2011
8003524	Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provi...	08/23/2011
7902069	Small area, robust silicon via structure and process A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductiv...	03/08/2011
7892968	Via gouging methods and related semiconductor structure Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material an...	02/22/2011
7884013	Dual damascene with via liner A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in t...	02/08/2011
7884014	Method of forming contact structure with contact spacer and method of fabricating semiconductor device using the same A method of forming a contact structure with a contact spacer and a method of fabricating a semiconductor device using the same. In the method of forming a contact structure, an interlayer dielectric layer is formed on a semiconductor substrate. The interlayer diele...	02/08/2011
7867894	Method for producing substrate A metallic film 43 that becomes the matrix of pad 32 is formed on semiconductor substrate 41. Next, through hole 31 is formed in the semiconductor substrate 41 facing the metallic film 43 at the portion corresponding to an a...	01/11/2011
7816257	Methods of fabricating semiconductor devices including contact plugs having laterally extending portions In a method of forming an integrated circuit device, an opening is formed extending through a first and a second insulating layers and through a semiconductor layer therebetween to a surface of a substrate. The opening includes a recess in a sidewall thereof between...	10/19/2010
7795139	Method for manufacturing semiconductor package A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; form...	09/14/2010
7781332	Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneat...	08/24/2010
7723229	Process of forming a self-aligned contact in a semiconductor device A process is implemented to form a contact opening in a semiconductor device that includes a gate electrode on a substrate, a spacer on a sidewall of the gate electrode and a dielectric material covering the gate electrode. The process comprises forming a photoresis...	05/25/2010
7691741	Method of forming bit line in semiconductor device A method of forming a bit line of a semiconductor device wherein an etch-stop nitride film, a trench oxide film and a hard mask nitride film are formed on a semiconductor substrate. The hard mask nitride film and the trench oxide film are etched to a limited etch th...	04/06/2010
7670948	Semiconductor device having diffusion barriers and a method of preventing diffusion of copper in a metal interconnection of a semiconductor device Embodiments of a semiconductor device and a method of fabricating the same may include an insulating layer formed on a substrate and having a predetermined hole, a metal interconnection formed in the hole and protruding relative to the insulating layer, a first barr...	03/02/2010
7651942	Metal interconnect structure and method A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying...	01/26/2010
7585766	Methods of manufacturing copper interconnect systems An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ...	09/08/2009
7576001	Manufacturing method for semiconductor device A semiconductor device manufacturing method for suppressing surface roughness of a Low-k insulating film during etching. In a laminated structure comprising a layer having formed thereon a lower copper wiring, a SiC film and a SiOC film, a via and an upper copper wi...	08/18/2009
7572729	Method of manufacturing semiconductor device A method of manufacturing semiconductor devices, including the steps of forming an insulating layer on a semiconductor substrate in which predetermined structures are formed, and etching the insulating layer to expose a predetermined region of the semiconductor subs...	08/11/2009
7550379	Alignment mark, use of a hard mask material, and method In a method to produce an alignment mark, an oxide layer and sacrificial layer are processed to comprise recesses. The recesses are filled with a filler material. During filling the recesses, a layer of filler material is formed on the sacrificial layer. The layer o...	06/23/2009
7531450	Method of fabricating semiconductor device having contact hole with high aspect-ratio Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper...	05/12/2009
7494922	Small electrode for phase change memories A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is substantially circular and an exposed surface that has a sublithographic dimension in a direction parallel to the exp...	02/24/2009
7491641	Method of forming a conductive line and a method of forming a conductive contact adjacent to and insulated from a conductive line This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first...	02/17/2009
7476614	Method of fabricating semiconductor device A method of fabricating a semiconductor device comprises sequentially forming a first conductive layer, a first insulating interlayer, a second conductive layer, and a second insulating interlayer on a semiconductor substrate. A mask layer is formed on the second in...	01/13/2009
7439144	CMOS gate structures fabricated by selective oxidation A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with convention...	10/21/2008
7435679	Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during...	10/14/2008
7435673	Methods of forming integrated circuit devices having metal interconnect structures therein Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insul...	10/14/2008
7435676	Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is...	10/14/2008
7410892	Methods of fabricating integrated circuit devices having self-aligned contact structures An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first in...	08/12/2008
7402514	Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the step...	07/22/2008
7402515	Method of forming through-silicon vias with stress buffer collars and resulting devices A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed. ...	07/22/2008
7396762	Interconnect structures with linear repair layers and methods for forming such interconnection structures Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a condu...	07/08/2008
7393779	Shrinking contact apertures through LPD oxide Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to t...	07/01/2008
7389581	Method of forming compliant contact structures A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the sub...	06/24/2008
7387961	Dual damascene with via liner A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in t...	06/17/2008
7381638	Fabrication technique using sputter etch and vacuum transfer First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the...	06/03/2008
7378339	Barrier for use in 3-D integration of circuits A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circ...	05/27/2008
7371677	Laterally grown nanotubes and method of formation A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portio...	05/13/2008

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Class 438/639 - Having viahole with sidewall component