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| Number | Title | Issue Date |
| 8173541 | Chip carrier substrate including capacitor and method for fabrication thereof A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect wit... | 05/08/2012 |
| 8110497 | Method for manufacturing semiconductor device An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection f... | 02/07/2012 |
| 8105941 | Through-wafer interconnection A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the back... | 01/31/2012 |
| 8093150 | Methods of manufacturing semiconductor devices and structures thereof Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material lay... | 01/10/2012 |
| 8084358 | Semiconductor device and manufacturing method thereof In a manufacturing method of a semiconductor device, an insulating film is formed on a first conductive film. By using a mask film having an opening that exposes the insulating film, anisotropic etching is performed to form a recess is formed in an upper part of the... | 12/27/2011 |
| 8080473 | Method for metallizing a pattern in a dielectric film A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiOx) layer formed on the SiCOH-containing la... | 12/20/2011 |
| 8062971 | Dual damascene process Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench ... | 11/22/2011 |
| 8062972 | Semiconductor process A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is remove... | 11/22/2011 |
| 8053359 | Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric laye... | 11/08/2011 |
| 7985677 | Method of manufacturing semiconductor device One of methods of manufacturing a semiconductor device of the present invention is as follows: a first conductive layer is formed, a first insulating layer is formed over the first conductive layer, and a second insulating layer is formed over the first insulating l... | 07/26/2011 |
| 7972957 | Method of making openings in a layer of a semiconductor device A method of making a semiconductor device including forming a first sacrificial layer over a first layer to be etched, the first sacrificial layer having a plurality of openings formed therethrough exposing a portion of the first layer; forming a first photoresist l... | 07/05/2011 |
| 7968454 | Method of forming pattern structure A method of forming a pattern structure includes forming a thin film pattern on a substrate, the thin film pattern including depression portions with first bottom widths, forming a protection layer on the thin film pattern by implanting ions into the thin film patte... | 06/28/2011 |
| 7955970 | Semiconductor device manufacturing method A process for producing a semiconductor device, comprising the wiring region forming step of forming a wiring region on a semiconductor substrate; the copper wiring layer forming step of forming a copper wiring layer on the formed wiring region by electrolytic plati... | 06/07/2011 |
| 7879718 | Local interconnect having increased misalignment tolerance A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter... | 02/01/2011 |
| 7879719 | Interconnect structure and method of manufacturing the same A semiconductor device and a method for manufacturing the device that minimizes a line width while maximizing integration density of the semiconductor device. The method includes forming an interlayer insulating film on a semiconductor substrate, and then forming a ... | 02/01/2011 |
| 7867893 | Method of forming an SOI substrate contact A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region s... | 01/11/2011 |
| 7838416 | Method of fabricating phase change memory cell A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension par... | 11/23/2010 |
| RE41935 | Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially throug... | 11/16/2010 |
| 7829459 | Method and apparatus for strapping two polysilicon lines in a semiconductor integrated circuit device A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. T... | 11/09/2010 |
| 7811930 | Manufacturing method of dual damascene structure A manufacturing method of a dual damascene structure is provided. First, a first dielectric layer, a second dielectric layer, and a mask layer are formed. A first trench structure is formed in the mask layer. A via structure is formed in the mask layer, the second d... | 10/12/2010 |
| 7767578 | Damascene interconnection structure and dual damascene process thereof A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide... | 08/03/2010 |
| 7749897 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a ... | 07/06/2010 |
| 7737029 | Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first e... | 06/15/2010 |
| 7704876 | Dual damascene interconnect structures having different materials for line and via conductors Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those us... | 04/27/2010 |
| 7704877 | Method of manufacturing semiconductor device and control system When a multi-layer structure is formed by forming the interconnect trenches or via holes having different patterns in a plurality of insulating films, an anti-reflective film and an upper resist film are stacked in this order over an insulating interlayer, and the a... | 04/27/2010 |
| 7700478 | Intermediate anneal for metal deposition The present teachings and illustrations describe a process for forming a plurality of conductive structures in or on a substrate. In one embodiment, the process comprises forming a plurality of recesses in or on the substrate, wherein the plurality of recesses inclu... | 04/20/2010 |
| 7691740 | Semiconductor device and method of fabricating same The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close t... | 04/06/2010 |
| 7687395 | Contact aperture and contact via with stepped sidewall and methods for fabrication thereof A semiconductor structure includes a semiconductor device including a contact region. The semiconductor structure also includes a passivation layer passivating the semiconductor device including the contact region. A narrow bottomed stepped sidewall contact aperture... | 03/30/2010 |
| 7682967 | Method of forming metal wire in semiconductor device A method of forming a metal wire in a semiconductor device is disclosed The method includes the steps of etching an insulating layer formed on a semiconductor substrate to form a dual damascene pattern, forming a barrier metal layer in the dual damascene pattern, fo... | 03/23/2010 |
| 7659196 | Soluble hard mask for interlayer dielectric patterning Described herein are embodiments of a method that includes forming a hard mask over an interlayer dielectric layer, patterning said hard mask, etching said interlayer dielectric layer, and removing said hard mask during a post-etch clean with a wet etchant having a ... | 02/09/2010 |
| 7655562 | Method of manufacturing semiconductor memory device A method of manufacturing a semiconductor device is disclosed. In the method of manufacturing the semiconductor device, a first insulating layer is formed on a semiconductor substrate. A metal line layer and an etch-stop layer are formed over the first insulating la... | 02/02/2010 |
| 7655561 | Method for making an opening for electrical contact by etch back profile control A method and apparatus for etchback profile control. The method includes performing a first etch through a first dielectric layer to form a first via and a second dielectric layer, filling the first via with a BARC material to form a first BARC layer, and performing... | 02/02/2010 |
| 7638426 | Semiconductor devices and methods of manufacturing the same Shorting of a copper line with an adjacent line in a semiconductor device during chemical mechanical polishing may be prevented and thus reliability of the semiconductor device may be improved, when the semiconductor device includes a substrate, an interlayer insula... | 12/29/2009 |
| 7618889 | Dual damascene fabrication with low k materials The invention provides methods and apparatuses for fabricating a dual damascene structure on a substrate. First, trench lithography and trench patterning are performed on the surface of a substrate to etch a low-k dielectric material layer to a desired etch depth to... | 11/17/2009 |
| 7601635 | Method of manufacturing a semiconductor device For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a polycrystalline silicon film, a tungsten silicide film and an insulating film s... | 10/13/2009 |
| 7569480 | Semiconductor devices and methods of fabricating the same In a method of fabricating a semiconductor device, a first mask pattern is formed on a substrate. The first mask pattern has a first opening formed to expose the substrate. An oxidation barrier region is formed in the substrate exposed by the first opening, and the ... | 08/04/2009 |
| 7563710 | Method of fabrication of interconnect structures A method of forming a damascene wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; rec... | 07/21/2009 |
| 7557035 | Method of forming semiconductor devices by microwave curing of low-k dielectric films The invention provides a method of exposing low-k dielectric films to microwave radiation to cure the dielectric films. Microwave curing reduces the cure-time necessary to achieve the desired mechanical properties in the low-k films, thus decreasing the thermal expo... | 07/07/2009 |
| 7553761 | Method of fabricating semiconductor device A method of fabricating a semiconductor device is provided. The method includes forming a low-k dielectric layer on a semiconductor substrate, forming a mask pattern on the low-k dielectric layer, and dry etching the low-k dielectric layer using the mask pattern as ... | 06/30/2009 |
| 7544608 | Porous and dense hybrid interconnect structure and method of manufacture A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense ... | 06/09/2009 |
