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| Number | Title | Issue Date |
| 7968452 | Titanium-based high-K dielectric films This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed us... | 06/28/2011 |
| 7892964 | Vapor deposition methods for forming a metal-containing layer on a substrate Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carb... | 02/22/2011 |
| 7833900 | Interconnections for integrated circuits including reducing an overburden and annealing The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of... | 11/16/2010 |
| 7829457 | Protection of conductors from oxidation in deposition chambers In some embodiments, after depositing conductive material on substrates in a deposition chamber, a reducing gas is introduced into as the chamber in preparation for unloading the substrates. The deposition chamber can be a batch CVD chamber and the deposited materia... | 11/09/2010 |
| 7491638 | Method of forming an insulating capping layer for a copper metallization layer A new technique is disclosed in which a barrier/capping layer for a copper-based metal line is formed by using a thermal-chemical treatment followed by an in situ plasma-based deposition of silicon nitride and/or silicon carbon nitride. The thermal-chemical treatmen... | 02/17/2009 |
| 7425480 | Semiconductor device and method of manufacture thereof A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode i... | 09/16/2008 |
| 7413985 | Method for forming a self-aligned nitrogen-containing copper silicide capping layer in a microstructure device By forming a copper/silicon/nitrogen alloy in a surface portion of a copper-containing region on the basis of a precursor layer, highly controllable and reliable process conditions may be established. The precursor layer may be formed on the basis of a liquid precur... | 08/19/2008 |
| 7358171 | Method to chemically remove metal impurities from polycide gate sidewalls An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also... | 04/15/2008 |
| 7335606 | Silicide formed from ternary metal alloy films A NiSi layer over silicon that is thermally stable and can form even in the presence of oxides. The method of fabricating the nickel silicide layer includes providing a substrate comprising silicon, depositing a layer of at least a 3-component metal alloy comprising... | 02/26/2008 |
| 7332422 | Method for CuO reduction by using two step nitrogen oxygen and reducing plasma treatment A method for cleaning a copper interconnect after a chemical-mechanical polishing that comprises: a) treating the surface of said copper interconnect with a nitrogen and oxygen containing treatment; and b) without breaking vacuum, treating the copper interconnect wi... | 02/19/2008 |
| 7320734 | Plasma immersion ion implantation system including a plasma source having low dissociation and low minimum plasma voltage A system for processing a workpiece includes a plasma immersion ion implantation reactor with an enclosure having a side wall and a ceiling and defining a chamber, and a workpiece support pedestal within the chamber having a workpiece support surface facing the ceil... | 01/22/2008 |
| 7303946 | Method of manufacturing a semiconductor device using an oxidation process A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode i... | 12/04/2007 |
| 7303982 | Plasma immersion ion implantation process using an inductively coupled plasma source having low dissociation and low minimum plasma voltage A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpi... | 12/04/2007 |
| 7301190 | Structures and methods to enhance copper metallization Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a meta... | 11/27/2007 |
| 7297628 | Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etch Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielec... | 11/20/2007 |
| 7294563 | Semiconductor on insulator vertical transistor fabrication and doping process A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conform... | 11/13/2007 |
| 7291545 | Plasma immersion ion implantation process using a capacitively couple plasma source having low dissociation and low minimum plasma voltage A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking... | 11/06/2007 |
| 7288491 | Plasma immersion ion implantation process One method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber includes initially depositing a seasoning film on the interior surfaces of the plasma reactor chamber before the workpiece is introduced, by introducing a seasoning... | 10/30/2007 |
| 7285196 | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requir... | 10/23/2007 |
| 7282445 | Multiple seed layers for interconnects One embodiment of the present invention is a method for depositing two or more seed layers over a substrate, the substrate includes a patterned insulating layer which comprises at least one opening surrounded by a field, the at least one opening and the field being ... | 10/16/2007 |
| 7262505 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on... | 08/28/2007 |
| 7262130 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have... | 08/28/2007 |
| 7256069 | Wafer-level package and methods of fabricating A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantial... | 08/14/2007 |
| 7253441 | Method of manufacturing thin film transistor The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a s... | 08/07/2007 |
| 7253521 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits include networks of electrical components that are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper in combination with diffusion barriers, rather than aluminum, to form the wi... | 08/07/2007 |
| 7223676 | Very low temperature CVD process with independently variable conformality, stress and composition of the CVD layer A low temperature process for depositing a coating containing any of silicon, nitrogen, hydrogen or oxygen on a workpiece includes placing the workpiece in a reactor chamber facing a processing region of the chamber, introducing a process gas containing any of silic... | 05/29/2007 |
| 7220665 | H plasma treatment Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive l... | 05/22/2007 |
| 7217667 | Processes for forming electronic devices including a semiconductor layer An impurity can be introduced into a semiconductor layer of a workpiece to affect the oxidation and the relative concentration of one element with respect to another element within the semiconductor layer. The impurity can be selectively implanted using one or more ... | 05/15/2007 |
| 7211512 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate. This method includes depositing a thin film seed layer of Palladium (Pd) or Cop... | 05/01/2007 |
| 7199052 | Seed layers for metallic interconnects One embodiment of the present invention is a method for making copper or a copper alloy interconnects, which method includes: (a) forming a patterned insulating layer over a substrate, the patterned insulating layer including at least one opening and a field surroun... | 04/03/2007 |
| 7198967 | Active matrix type semiconductor display device There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potent... | 04/03/2007 |
| 7183223 | Methods for forming small contacts Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact ho... | 02/27/2007 |
| 7183177 | Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, includes forming an oxide layer on at least a first surface of a first one of the wafers and performing a bonding enhancement implantation step by ion implantation of... | 02/27/2007 |
| 7172958 | High-frequency wiring structure and method for producing the same A high-frequency wiring structure includes a microstrip line having a ground conductor, a dielectric disposed on the ground conductor, and a transmission conductor that is at least partially disposed in the dielectric. The transmission conductor is defined by a flat... | 02/06/2007 |
| 7166524 | Method for ion implanting insulator material to reduce dielectric constant An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielec... | 01/23/2007 |
| 7160776 | Methods of forming a gate structure of a non-volatile memory device and apparatus for performing the same Methods of forming a gate structure of a non-volatile memory device include forming a gate pattern having a control gate on a semiconductor substrate. An oxidation-preventing layer is formed on the control gate in a process chamber while maintaining a substantially ... | 01/09/2007 |
| 7151018 | Method and apparatus for transistor sidewall salicidation A method for manufacturing a transistor is provided. The transistor has a substrate with an insulator on the substrate. A structure on the insulator having a structure sidewall is provided with spacers covering a portion of the structure sidewall. An exposed portion... | 12/19/2006 |
| 7148158 | Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film... | 12/12/2006 |
| 7144808 | Integration flow to prevent delamination from copper The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer... | 12/05/2006 |
| 7141511 | Method and apparatus for fabricating a memory device with a dielectric etch stop layer The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS ... | 11/28/2006 |
