Did You Know...
...that when IBM conducted a market study of Chester Carlson's invention in 1959, the company concluded that it would take only 5000 units of his new product to saturate the market? IBM therefore declined to be part of the new product introduction. Too bad for IBM. Carlson's invention was the xerography process, and his new product was the beginning of the Xerox Corporation. It is estimated that every day, worldwide, 3,000,000,000 copies are made!!
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| Number | Title | Issue Date |
| 8178439 | Surface cleaning and selective deposition of metal-containing cap layers for semiconductor devices A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a... | 05/15/2012 |
| 8124526 | Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroe... | 02/28/2012 |
| 8119522 | Method of fabricating damascene structures Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; ... | 02/21/2012 |
| 8053357 | Prevention of post CMP defects in CU/FSG process A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silica... | 11/08/2011 |
| 7951706 | Method of manufacturing metal interconnection A method of manufacturing a semiconductor is provided. A fist metal layer can be formed on a lower structural layer, and an interlayer metal dielectric (IMD) layer can be formed on the first metal layer. A sacrificial oxide layer can be formed on the IMD layer, and ... | 05/31/2011 |
| 7947596 | Semiconductor device and method of manufacturing the same A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingre... | 05/24/2011 |
| RE41842 | Methods of forming electrical interconnects on integrated circuit substrates using selective slurries Methods of forming electrical interconnects include the steps of forming a first electrically conductive layer on a semiconductor substrate and then forming a first electrically insulating layer on the first electrically conductive layer. A second electrically insul... | 10/19/2010 |
| 7696086 | Fabricating method of an interconnect structure An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plu... | 04/13/2010 |
| 7674708 | Method for forming fine patterns of a semiconductor device A method for forming a fine pattern of a semiconductor device overcomes resolution limits of exposure equipment. The method includes forming a first photoresist pattern over an underlying layer formed over a semiconductor substrate. An amorphous carbon film and a se... | 03/09/2010 |
| 7662714 | Method for forming metal line of semiconductor device A method for forming a metal line of a semiconductor device uses a low dielectric constant material as an interlayer dielectric layer and treats a surface of the interlayer dielectric layer with plasma to prevent moisture and ammonia from being adsorbed in the low d... | 02/16/2010 |
| 7608536 | Method of manufacturing contact opening Disclosed is a method of manufacturing a semiconductor device, in which a high-temperature SOD (spin on dielectric) annealing process is performed to prevent a SOD crack, and a nitride film, serving as a capping layer, is formed over the entire surface of a bit line... | 10/27/2009 |
| 7605074 | Chemical mechanical polishing and method for manufacturing semiconductor device using the same Provided is a CMP method. According to the CMP method, an interlayer insulating layer having two or more layers is etched to form a trench and/or via hole, and a combined thickness of the two or more layers are measured. A barrier metal layer and a metal layer are s... | 10/20/2009 |
| 7595263 | Atomic layer deposition of barrier materials Methods for processing substrate to deposit barrier layers of one or more material layers by atomic layer deposition are provided. In one aspect, a method is provided for processing a substrate including depositing a metal nitride barrier layer on at least a portion... | 09/29/2009 |
| 7550378 | Method of manufacturing a semiconductor device having a cell area with a high device element density A method for manufacturing a semiconductor device including providing a semiconductor substrate including a cell area formed with relatively high device element density and a scribe line area formed with a device element density lower than the device element density... | 06/23/2009 |
| 7531447 | Process for forming integrated circuit comprising copper lines An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% crystal orientation and a less than 20% crystal orientation. ... | 05/12/2009 |
| 7507657 | Method for fabricating storage node contact in semiconductor device Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and planarizing cruspidal patterns caused during a storage node contact isolation process. In accordance with ... | 03/24/2009 |
| 7494921 | Aluminum metal line of a semiconductor device and method of fabricating the same A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal ... | 02/24/2009 |
| 7435673 | Methods of forming integrated circuit devices having metal interconnect structures therein Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insul... | 10/14/2008 |
| 7432191 | Method of forming a dual damascene structure utilizing a developable anti-reflective coating A method of patterning a structure in a thin film on a substrate is described. A film stack on the substrate includes the thin film on the substrate, a developable anti-reflective coating (ARC) layer on the thin film, and a first photo-resist layer on the developabl... | 10/07/2008 |
| 7413989 | Method of manufacturing semiconductor device A semiconductor wafer including an underlying layer including an insulating film having at least one recess therein and a metallic material layer formed over a top surface of the underlying layer and filling the recess, on a semiconductor substrate, is subjected to ... | 08/19/2008 |
| 7399697 | Very low dielectric constant plasma-enhanced CVD films The present invention provides a method for depositing nano-porous low dielectric constant films by reacting a mixture comprising an oxidizable silicon component and an oxidizable component having thermally labile groups with an oxidizing gas in gas-phase plasma-enh... | 07/15/2008 |
| 7399671 | Disposable pillars for contact formation Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between ... | 07/15/2008 |
| 7381638 | Fabrication technique using sputter etch and vacuum transfer First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the... | 06/03/2008 |
| 7375023 | Method and apparatus for chemical mechanical polishing of semiconductor substrates Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material a... | 05/20/2008 |
| 7372154 | Semiconductor device As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked ... | 05/13/2008 |
| 7371653 | Metal interconnection structure of semiconductor device and method of forming the same Provided is a metal interconnection structure of a semiconductor device, having: a lower metal layer disposed on an insulating layer formed on a semiconductor device; a contact plug disposed on the lower metal layer; a supporting layer disposed to surround the conta... | 05/13/2008 |
| 7372160 | Barrier film deposition over metal for reduction in metal dishing after CMP A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to patt... | 05/13/2008 |
| 7371665 | Method for fabricating shallow trench isolation layer of semiconductor device A method for fabricating an STI layer of a semiconductor device is disclosed, to improve the integration of the semiconductor device in a method of increasing a moat area for a gate line by minimizing an isolation area between moat areas, which includes the steps of... | 05/13/2008 |
| 7371679 | Semiconductor device with a metal line and method of forming the same A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing the IMD layer through a first CMP process, and patterning a via hole on... | 05/13/2008 |
| 7368393 | Chemical oxide removal of plasma damaged SiCOH low k dielectrics A method for removing damages of a dual damascene structure after plasma etching is disclosed. The method comprises the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged r... | 05/06/2008 |
| 7368066 | Gold CMP composition and method The invention provides a cyanide-free chemical-mechanical polishing (CMP) composition useful for polishing a gold-containing surface of a substrate. The CMP composition comprises an abrasive, a gold-oxidizing agent, a cyanide-free gold-solubilizing agent, and an aqu... | 05/06/2008 |
| 7368383 | Hillock reduction in copper films A method for treating a copper surface of a semiconductor device provides exposing the copper surface to a citric acid solution after the surface is formed using CMP (chemical mechanical polishing) or other methods. The citric acid treatment may take place during a ... | 05/06/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7365430 | Semiconductor device and method of manufacturing the same Disclosed herein is a semiconductor device and method of manufacturing the same. A step between a memory cell formed in a cell region and a transistor formed in a peripheral circuit region is minimized, and the height of a gate in the memory cell is minimized. Accor... | 04/29/2008 |
| 7365009 | Structure of metal interconnect and fabrication method thereof A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric condu... | 04/29/2008 |
| 7364835 | Developer-soluble materials and methods of using the same in via-first dual damascene applications Wet-recess (develop) gap-fill and bottom anti-reflective coatings based on a polyamic acid or polyester platform are provided. The polyamic acid platform allows imidization to form a polyimide when supplied with thermal energy. The gap-fill and bottom anti-reflectiv... | 04/29/2008 |
| 7361603 | Passivative chemical mechanical polishing composition for copper film planarization A CMP composition containing 5-aminotetrazole, e.g., in combination with oxidizing agent, chelating agent, abrasive and solvent and a method of use. Such CMP composition may be diluted during the CMP polish to minimize the occurrence of dishing or other adverse plan... | 04/22/2008 |
| 7361575 | Semiconductor device and method for manufacturing the same Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device that may be capable of improving a step coverage of main chip and scribe lane regions during a formation of an interlayer dielectric are provided. In embodiments, the ... | 04/22/2008 |
| 7361974 | Manufacturing method for an integrated semiconductor structure The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a... | 04/22/2008 |
| 7361322 | Ceric oxide and method for production thereof, and catalyst for exhaust gas clarification The present invention relates to ceric oxide that has excellent heat resistance and oxygen absorbing and desorbing capability useful as a co-catalyst material suitable for a catalyst for purifying exhaust gas, that is capable of maintaining a large specific surface ... | 04/22/2008 |
