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| Number | Title | Issue Date |
| 8124525 | Method of forming self-aligned local interconnect and structure formed thereby Embodiments of the present invention provide a method of forming local interconnect for semiconductor devices. The method includes depositing a blanket layer of conductive material over one or more semiconductor devices; creating a pattern of local interconnect cove... | 02/28/2012 |
| 8003521 | Semiconductor processing Devices, methods, and systems for semiconductor processing are described herein. A number of method embodiments of semiconductor processing can include forming a silicon layer on a structure, forming an opening through the silicon layer and into the structure, and s... | 08/23/2011 |
| 7985675 | Method for fabricating a semiconductor device that includes processing an insulating film to have an upper portion with a different composition than an other portion A semiconductor device includes: a semiconductor substrate; a first insulating film (third insulating film 24) formed on the semiconductor substrate, having a first trench (second interconnect trench 28), and having a composition ratio varying along th... | 07/26/2011 |
| 7915160 | Methods for forming small contacts Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact ho... | 03/29/2011 |
| 7897508 | Method to eliminate Cu dislocation for reliability and yield Embodiments in accordance with the present invention provide methods of forming a metal interconnect structure which avoid defects arising from copper migration. In accordance with particular embodiments, an electroplated copper feature is subjected to a brief therm... | 03/01/2011 |
| 7749894 | Integrated circuit processing system An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielec... | 07/06/2010 |
| 7727884 | Methods of forming a semiconductor device including a phase change material layer A method includes forming a phase change material layer on a substrate using a deposition process that employs a process gas. The process gas includes a germanium source gas, and the germanium source gas includes at least one of the atomic groups “—N═C═O”,... | 06/01/2010 |
| 7687393 | Polishing composition and rinse composition A polishing composition for reducing the haze level of the surface of silicon wafers contains hydroxyethyl cellulose, polyethylene oxide, an alkaline compound, water, and silicon dioxide. ... | 03/30/2010 |
| 7575997 | Method for forming contact hole of semiconductor device A method for forming a contact hole of a semiconductor is provided. Conductive patterns are formed over a substrate. An insulation layer is formed over the substrate to bury the conductive patterns. A hard mask including an amorphous carbon layer and an oxide based ... | 08/18/2009 |
| 7544606 | Method to implement stress free polishing A method of forming a metal feature in a low-k dielectric layer is provided. The method includes forming an opening in a low-k dielectric layer, forming a metal layer having a substantially planar surface over the low-k dielectric layer using spin-on method, and str... | 06/09/2009 |
| 7534719 | Method for reduction in metal dishing after CMP A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to patt... | 05/19/2009 |
| 7528064 | Interconnect structures with bond-pads and methods of forming bump sites on bond-pads Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads,... | 05/05/2009 |
| 7425501 | Semiconductor structure implementing sacrificial material and methods for making and implementing the same A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is pe... | 09/16/2008 |
| 7416985 | Semiconductor device having a multilayer interconnection structure and fabrication method thereof A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall s... | 08/26/2008 |
| 7407879 | Chemical planarization performance for copper/low-k interconnect structures An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. E... | 08/05/2008 |
| 7405154 | Structure and method of forming electrodeposited contacts A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the diel... | 07/29/2008 |
| 7405152 | Reducing wire erosion during damascene processing A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby str... | 07/29/2008 |
| 7399699 | On-die reflectance arrangements Improved semiconductor reflectance arrangements (e.g., semiconductor devices, systems including semiconductor devices, methods, etc.). ... | 07/15/2008 |
| 7399649 | Semiconductor light-emitting device and fabrication method thereof An underlying layer ALY of GaN is formed on a sapphire substrate SSB; a transfer layer TLY of GaN with a bump and dip shaped surface is formed on the underlying layer ALY; a light absorption layer BLY is formed on the bump and dip shaped surface of the transfer laye... | 07/15/2008 |
| 7399696 | Method for high performance inductor fabrication using a triple damascene process with copper BEOL A method of forming a high performance inductor comprises providing a substrate; forming a plurality of wiring levels over the substrate, wherein each of the wiring levels comprise a dielectric layer; forming a first trench having a first depth in a first dielectric... | 07/15/2008 |
| 7399671 | Disposable pillars for contact formation Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between ... | 07/15/2008 |
| 7396768 | Copper damascene chemical mechanical polishing (CMP) for thin film head writer fabrication In one method and embodiment of the present invention, at least one coil layer is formed in a write head, using a two-slurry step of copper damascene chemical mechanical polishing method with a first slurry step removing the undesirable copper that is on top of the ... | 07/08/2008 |
| 7387963 | Semiconductor wafer and process for producing a semiconductor wafer A semiconductor wafer has an edge region with no defects larger than or equal to 0.3 μm. The wafers are produced by a process, comprising (a) providing a semiconductor wafer having a rounded and etched edge; (b) polishing the edge of the semiconductor wafer, in whi... | 06/17/2008 |
| 7384865 | Semiconductor device with a metal line and method of forming the same A method of forming a metal line in a semiconductor device includes: forming a lower insulation layer for insulation from the lower substrate; forming a first metal line at a certain region on the lower insulation layer; sequentially forming a first oxide layer, an ... | 06/10/2008 |
| 7381638 | Fabrication technique using sputter etch and vacuum transfer First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the... | 06/03/2008 |
| 7382054 | Method for forming self-aligned contacts and local interconnects simultaneously The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconne... | 06/03/2008 |
| 7375023 | Method and apparatus for chemical mechanical polishing of semiconductor substrates Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material a... | 05/20/2008 |
| 7371679 | Semiconductor device with a metal line and method of forming the same A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing the IMD layer through a first CMP process, and patterning a via hole on... | 05/13/2008 |
| 7365003 | Carbon nanotube interconnects in porous diamond interlayer dielectrics A method and structure for using porous diamond interlayer dielectrics (ILDs) in conjunction with carbon nanotube interconnects is herein described. A diamond ILD is deposited on an underlaying layer. The diamond layer is optionally and selectively removed of non-sp... | 04/29/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7351653 | Method for damascene process Disclosed are methods for carrying out a damascene process in semiconductor fabrication including the steps of: forming an intermetal dielectric film on a semiconductor substrate; patterning the intermetal dielectric film and forming an intermetal dielectric pattern... | 04/01/2008 |
| 7348272 | Method of fabricating interconnect A method of fabricating interconnect is described. A first dielectric layer having an opening is formed over a substrate. A metal layer is filled into the opening. A material layer is formed over the first dielectric layer and the metal layer. A surface treatment pr... | 03/25/2008 |
| 7338907 | Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the e... | 03/04/2008 |
| 7338888 | Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, ... | 03/04/2008 |
| 7335965 | Packaging of electronic chips with air-bridge structures A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structur... | 02/26/2008 |
| 7323113 | Pattern transfer with self-similar sacrificial mask layer and vector magnetic field sensor A method is provided for producing a lithographic pattern using a mask that includes the same materials as the material to be etched, allowing the pattern to be transferred and the etch mask to be removed in one step. In accordance with features of the invention, th... | 01/29/2008 |
| 7323407 | Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a ... | 01/29/2008 |
| 7323386 | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m... | 01/29/2008 |
| 7316972 | Contact hole formation method A contact hole formation method includes a process of depositing a BPSG film 4 on a semiconductor substrate 1 on which transistors are formed, a process of planarizing the BPSG film 4, a process of depositing a dielectric film 5 on the BP... | 01/08/2008 |
| 7317208 | Semiconductor device with contact structure and manufacturing method thereof A plurality of gate lines are formed on a substrate. After depositing a gate insulating layer, a semiconductor layer and a doped amorphous silicon layer are sequentially formed thereon. A lower insulating layer made of silicon nitride and an upper insulating layer m... | 01/08/2008 |
