Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 6743683 | Polysilicon opening polish Fabricating a semiconductor structure includes providing a semiconductor substrate, forming a silicide layer over the substrate, and removing a portion of the silicide layer by chemical mechanical polishing. The fabrication of the structure can also include forming ... | 06/01/2004 |
| 6737346 | Integrated circuit with modified metal features and method of fabrication therefor Embodiments of the invention concern modifying the layout of one or more metal layers of an integrated circuit before patterning those layers, so that an intermetal dielectric layer (IDL) subsequently deposited over the top surface of the patterned layer will be sub... | 05/18/2004 |
| 6734097 | Liner with poor step coverage to improve contact resistance in W contacts A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned... | 05/11/2004 |
| 6727172 | Process to reduce chemical mechanical polishing damage of narrow copper lines A method of forming a narrow copper line structure, embedded in an opening in an insulator layer, in which the defect count of the narrow copper line structure is minimized, has been developed. The method features a combination of processes applied to a copper layer... | 04/27/2004 |
| 6723631 | Fabrication method of semiconductor integrated circuit device The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out i... | 04/20/2004 |
| 6723600 | Method for making a metal-insulator-metal capacitor using plate-through mask techniques A method for making a metal-insulator-metal capacitive structure includes depositing a copper barrier and seed layer over a support structure such as an inter-level dielectric layer, forming a dielectric over the copper barrier and seed layer, and then forming a for... | 04/20/2004 |
| 6716771 | Method for post-CMP conversion of a hydrophobic surface of a low-k dielectric layer to a hydrophilic surface A method of converting a hydrophobic surface of a dielectric layer to a hydrophilic surface is described. That method comprises forming on a substrate a dielectric layer that has a hydrophobic surface, then coupling a hydrophilic component to the surface of the diel... | 04/06/2004 |
| 6716743 | Method of manufacturing a semiconductor device A method of forming wiring of a uniform film thickness using a damascene process is proposed. Tantalum nitride, copper, another copper, and another tantalum nitride, for example, all constituting conductive films of different polishing rates, are overlayed on the to... | 04/06/2004 |
| 6716741 | Method of patterning dielectric layer with low dielectric constant The invention relates to a method for directly patterning a low-k dielectric layer by a high energy flow without using any photoresist layer, so that the exposed portion of the low-k dielectric layer is cured and becomes insoluble to the developing solution. The une... | 04/06/2004 |
| 6713385 | Implanting ions in shallow trench isolation structures Ions are implanted into the dielectric layer and/or barrier layer over a semiconductor substrate to change the polish rates of either or both layers during formation of a shallow trench isolation (STI) structure. The ion implantation can change or affect the polish ... | 03/30/2004 |
| 6713235 | Method for fabricating thin-film substrate and thin-film substrate fabricated by the method Supports (3) are formed to be arrayed on a support base (1), a sacrifice layer (15) is formed of a resin material, and the sacrifice layer (15) is planarized so as to expose the top of the respective supports (3), thereby forming a... | 03/30/2004 |
| 6709970 | Method for creating a damascene interconnect using a two-step electroplating process A method for forming void-free, low contact-resistance damascene interconnects during a manufacturing process of an integrated circuit having both narrow and deep openings and wide and shallow openings on a same substrate features a two-step copper (Cu) deposition p... | 03/23/2004 |
| 6709874 | Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation A semiconductor device (100) having a copper damascene BEOL structure. A metal cap layer (120) is formed over conductive lines (118) to prevent oxidation of the conductive lines (118) during subsequent processing steps. The metal cap laye... | 03/23/2004 |
| 6706629 | Barrier-free copper interconnect A new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an ... | 03/16/2004 |
| 6696358 | Viscous protective overlayers for planarization of integrated circuits The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The pres... | 02/24/2004 |
| 6693029 | Method of forming an insulative substrate having conductive filled vias A method for manufacturing a substrate, including adhering an adhesive layer to an organic insulation substrate to form a first part; forming a via hole in the first part such that the via hole penetrates the first part; forming a conductive metal film so... | 02/17/2004 |
| 6693028 | Semiconductor device having multilayer wiring structure and method for manufacturing the same A method for manufacturing a semiconductor device includes a step of forming a first groove in a first insulating film, forming a conductive film in the first groove, a step of selectively forming a second insulating film on the conductive film and the fi... | 02/17/2004 |
| 6692580 | Method of cleaning a dual damascene structure A method of cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer, exposing the first metal la... | 02/17/2004 |
| 6686286 | Method for forming a borderless contact of a semiconductor device A method for forming a borderless contact of a semiconductor device includes forming a gate electrode on a field oxide of the semiconductor substrate, patterning a stacked structure of a buffer layer and an etching barrier layer on sidewalls of the gate e... | 02/03/2004 |
| 6673718 | Methods for forming aluminum metal wirings An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surf... | 01/06/2004 |
| 6670274 | Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure A method of forming a planarized final copper structure including the following steps. A structure is provided having a patterned dielectric layer formed thereover. The patterned dielectric layer having an opening formed therein. A barrier layer is formed... | 12/30/2003 |
| 6664154 | Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes An exemplary embodiment relates to a method of using amorphous carbon in replacement gate integration processes. The method can include depositing an amorphous carbon layer above a substrate, patterning the amorphous carbon layer, depositing a dielectric ... | 12/16/2003 |
| 6660629 | Chemical mechanical polishing method for fabricating copper damascene structure A method of fabricating a copper damascene. The method is applicable to a substrate, which substrate has a dielectric layer formed thereon. The method comprising forming a damascene opening in the dielectric layer, forming a barrier layer which conforms t... | 12/09/2003 |
| 6656841 | Method of forming multi layer conductive line in semiconductor device The present invention relates to a method of forming a multi-layer conductive line in a semiconductor device. A portion of a contact of a lower conductive line is selectively etched by a given thickness. A sacrificial barrier layer is then formed on the e... | 12/02/2003 |
| 6656834 | Method of selectively alloying interconnect regions by deposition process A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffu... | 12/02/2003 |
| 6653732 | Electronic component having a semiconductor chip An electronic component includes a semiconductor chip and/or a test structure. The semiconductor chip includes a multi-layer coating having at least one interconnect layer, at least one insulation layer, and at least one planarization layer. A method of p... | 11/25/2003 |
| 6649515 | Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures A method of forming an interconnection including the steps of depositing a first masking material over a first conductive region of an integrated circuit substrate and depositing a dielectric material over the first masking material. The method also inclu... | 11/18/2003 |
| 6649513 | Copper back-end-of-line by electropolish A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least ... | 11/18/2003 |
| 6645851 | Method of forming planarized coatings on contact hole patterns of various duty ratios A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate a... | 11/11/2003 |
| 6639285 | Method for fabricating a semiconductor device A method for making a semiconductor device is provided. The method allows for depositing a layer of a doped dielectric. The method further allows for executing plasma etching so that one or more etchant gases flow over the layer of doped dielectric. A red... | 10/28/2003 |
| 6638863 | Electropolishing metal layers on wafers having trenches or vias with dummy structures In electropolishing a metal layer on a semiconductor wafer, a dielectric layer is formed on the semiconductor wafer. The dielectric layer is formed with a recessed area and a non-recessed area. A plurality of dummy structures are formed within the recesse... | 10/28/2003 |
| 6638851 | Dual hardmask single damascene integration scheme in an organic low k ILD Process of making a semiconductor using dual inorganic hardmask in single damascene process integration scheme in an organic low k interlayer dielectric (ILD) by: providing semiconductor substrate; depositing organic low k ILD layer on substrate; f... | 10/28/2003 |
| 6635586 | Method of forming a spin-on-glass insulation layer A method of forming a SOG insulation layer of a semiconductor device comprises forming the SOG insulation layer on a substrate having a stepped pattern by using a polysilazane in a solution state, performing a pre-bake process for removing solvent element... | 10/21/2003 |
| 6635562 | Methods and solutions for cleaning polished aluminum-containing layers Methods for making an aluminum-containing metallization structure, methods and solutions for cleaning a polished aluminum-containing layer, and the structures formed by these methods. The methods for making the aluminum-containing metallization structure ... | 10/21/2003 |
| 6627539 | Method of forming dual-damascene interconnect structures employing low-k dielectric materials Interconnects in sub-micron and sub-half-micron integrated circuit devices are fabricated using a dual damascene process incorporating a low-k dielectric. A dual-damascene structure can be implemented without the necessity of building a single damascene b... | 09/30/2003 |
| 6617241 | Method of thick film planarization Planarization of the top surfaces of layers that are more than about a micron thick is beset with problems not encountered in thinner layers. These problems have been overcome by means of a process that, initially allows the formation of `horns` in the su... | 09/09/2003 |
| 6613594 | Surface plasmon resonance-based endpoint detection for chemical mechanical planarization (CMP) A method is provided, the method comprising planarizing a dielectric layer disposed above a structure layer, exciting surface plasmons in a conductive film disposed in the dielectric layer and detecting photons reflected from the conductive film to determ... | 09/02/2003 |
| 6607955 | Method of forming self-aligned contacts in a semiconductor device A method of forming self-aligned contacts in a semiconductor device wherein a silicon nitride layer and a polysilicon layer are formed on a gate electrode layer. The polysilicon layer, the silicon nitride layer, and the gate electrode layer are etched to ... | 08/19/2003 |
| 6600229 | Planarizers for spin etch planarization of electronic components An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer co... | 07/29/2003 |
| 6596639 | Method for chemical/mechanical planarization of a semiconductor wafer having dissimilar metal pattern densities The present invention provides a method of manufacturing an integrated circuit including planarizing a semiconductor wafer surface. In one embodiment, the method comprises forming a dielectric layer over a first level having an irregular topography, depos... | 07/22/2003 |
