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"During my service in the United States Congress, I took the initiative in creating the Internet."
Al Gore ; The basis for the later misquote by US Republicans that Gore had "invented" the Internet. Gore was the leading political champion of the modern-day Internet.
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| Number | Title | Issue Date |
| 4917759 | Method for forming self-aligned vias in multi-level metal integrated circuits A process for forming a via in a semiconductor device using a self-aligned metal pillar to connect metal layers separated by a dielectric. A first aluminum layer is formed on an oxide layer overlying a semiconductor substrate, and a thin tungsten layer is... | 04/17/1990 |
| 4879257 | Planarization process A method for forming a multilayer integrated circuit is described wherein the resultant top surface thereof is substantially planar. The method involves first forming a layer of connecting metallization on integrated circuit components formed in a convent... | 11/07/1989 |
| 4824521 | Planarization of metal pillars on uneven substrates A method for forming vertical metal interconnects on a semiconductor substrate having an uneven surface comprises first forming a laminated metal structure over the entire substrate. The laminated metal structure includes a first metallization sublayer, a... | 04/25/1989 |
| 4800176 | Method for forming contact portion in semiconductor integrated circuit devices A method of manufacturing semiconductor devices according to the present invention includes the steps of forming an element isolation region on the main surface of a semiconductor substrate of a first conductivity type, forming a high impurity concentrati... | 01/24/1989 |
| 4795722 | Method for planarization of a semiconductor device prior to metallization A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patternin... | 01/03/1989 |
| 4758306 | Stud formation method optimizing insulator gap-fill and metal hole-fill A method of forming a conductive structure on a substrate by using both of the via-filling and stud-forming metallization techniques. A stud that is approximately one-half the thickness of the final stud is defined on a conductive layer. The stud-forming ... | 07/19/1988 |
| 4753709 | Method for etching contact vias in a semiconductor device A method for forming contact vias in order to make electrical connection between conductive interconnection layers is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techn... | 06/28/1988 |
| 4710398 | Semiconductor device and manufacturing method thereof A method of manufacturing a semiconductor device. An insulation film having an opening is formed on a semiconductor substrate. The opening is filled with an electrically conductive material so as to substantially flatten the top surface of the opening fil... | 12/01/1987 |
| 4674176 | Planarization of metal films for multilevel interconnects by pulsed laser heating In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small ... | 06/23/1987 |
| 4670091 | Process for forming vias on integrated circuits In a process of forming vias for multilevel interconnects used in integrated circuits, a layer of a first metal is formed on a semiconductor substrate. A layer of a second metal is formed on the first metal layer. The second metal layer is etched in a pre... | 06/02/1987 |
| 4614021 | Pillar via process An improved means and method is described for providing a conductive pillar in a via between multiple layers of conductors on planar electronic structures such as integrated circuits. A lower first conductor layer is formed on the device substrate and cov... | 09/30/1986 |
| 4541893 | Process for fabricating pedestal interconnections between conductive layers in an integrated circuit A process for fabricating pedestal interconnections between conductive layers in an integrated circuit includes the steps of (a) forming a first conductive layer over a semiconductor substrate; (b) applying a stop etch layer to said first conductive layer... | 09/17/1985 |
| 4541169 | Method for making studs for interconnecting metallization layers at different levels in a semiconductor chip Disclosed herein is a method enabling the use of four or more levels of metal over silicon chips whereby increased wiring density, reduced wiring capacitances and improved interconnection reliability are achieved. Stud vertical wiring and special etching ... | 09/17/1985 |
| 4396458 | Method for forming planar metal/insulator structures Formation of planar conductor/insulator semiconductor devices utilizing hafnium coated aluminum based metallization with a magnesium oxide mask for dry etching of the metallization and deposition of planar insulation. The hafnium coating is used to protect the... | 08/02/1983 |
