Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 8129268 | Self-aligned lower bottom electrode A method of fabricating a lower bottom electrode for a memory element and a semiconductor structure having the same includes forming a dielectric layer over a semiconductor substrate having a plurality of conductive contacts formed therein to be connected to access ... | 03/06/2012 |
| 8119519 | Semiconductor device manufacturing method A method for making a semiconductor device including at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections prov... | 02/21/2012 |
| 8084356 | Methods of low-K dielectric and metal process integration An integrated process for forming metallization layers for electronic devices that use damascene structures that include low-k dielectric and metal. According to one embodiment of the present invention, the integrated process includes planarizing a gapfill metal in ... | 12/27/2011 |
| 8043959 | Method of forming a low-k dielectric layer with improved damage resistance and chemical integrity A method of forming a low-k dielectric layer or film includes forming a porous low-k dielectric layer or film over a wafer or substrate. Active bonding is introduced into the porous low-k dielectric layer or film to improve damage resistance and chemical integrity o... | 10/25/2011 |
| 8003517 | Method for forming interconnects for 3-D applications A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion... | 08/23/2011 |
| 7928003 | Air gap interconnects using carbon-based films A method of forming an interconnect structure comprising: forming a sacrificial inter-metal dielectric (IMD) layer over a substrate, wherein the sacrificial IMD layer comprising a carbon-based film, such as amorphous carbon, advanced patterning films, porous carbon,... | 04/19/2011 |
| 7829454 | Method for integrating selective ruthenium deposition into manufacturing of a semiconductior device A method for integrating selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu. The method includes selectively depositing a Ru metal film on a metallization layer or on bulk Cu using a ... | 11/09/2010 |
| 7811927 | Method of manufacturing metal line A method of manufacturing a metal line according to embodiments includes forming an interlayer dielectric layer over a semiconductor substrate. A dielectric layer is formed over the interlayer dielectric layer. A trench may be formed by etching the dielectric layer ... | 10/12/2010 |
| RE41697 | Method of forming planarized coatings on contact hole patterns of various duty ratios A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate and baked at... | 09/14/2010 |
| 7790604 | Krypton sputtering of thin tungsten layer for integrated circuits A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering depos... | 09/07/2010 |
| 7696085 | Dual damascene metal interconnect structure having a self-aligned via A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region a... | 04/13/2010 |
| 7635644 | Semiconductor device including metal interconnection and method for forming metal interconnection Disclosed are a method for forming a metal interconnection and a semiconductor device including the metal interconnection. The method includes the steps of forming a slope by etching a corner of a contact hole, which exposes a predetermined pattern formed on a subst... | 12/22/2009 |
| 7585760 | Method for forming planarizing copper in a low-k dielectric Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e.g., aluminum) over first conductive film (e.g., copper) deposited in an opening formed in a dielectric layer (e.g., low-k dielectric). The second conductive fil... | 09/08/2009 |
| 7585761 | Manufacturing method of semiconductor device It is an object of the present invention to suppress an influence of voltage drop due to wiring resistance to make an image quality of a display device uniform. In addition, it is also an object of the present invention to suppress delay due to a wiring for electric... | 09/08/2009 |
| 7582556 | Circuitry component and method for forming the same A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and... | 09/01/2009 |
| 7566652 | Electrically inactive via for electromigration reliability improvement A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second dielectric layer 308 is formed over the first dielectric layer 302 | 07/28/2009 |
| 7560378 | Method for manufacturing semiconductor device A diffusion barrier film, a second insulating film, and a cap film are sequentially laminated on a first insulating film over a substrate. A wiring trench portion is formed extending therethrough to the first insulating film, assuming that the ratio of a width of th... | 07/14/2009 |
| 7557031 | Etch back with aluminum CMP for LCOS devices A method for manufacturing an LCOS device includes forming an interlayer dielectric layer overlying a surface region of a substrate. The interlayer dielectric layer is patterned to form a plurality of recessed regions. Each of the recessed regions corresponds to a p... | 07/07/2009 |
| 7485571 | Method of making an integrated circuit General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 02/03/2009 |
| 7473636 | Method to improve time dependent dielectric breakdown In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with ... | 01/06/2009 |
| 7446033 | Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried... | 11/04/2008 |
| 7439179 | Healing detrimental bonds in deposited materials A method for healing detrimental bonds in deposited materials, for example porous, low-k dielectric materials, including oxydatively processing a deposited material, processing the deposited material with a trialkyl group III compound, and processing in the presence... | 10/21/2008 |
| 7416985 | Semiconductor device having a multilayer interconnection structure and fabrication method thereof A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall s... | 08/26/2008 |
| 7407879 | Chemical planarization performance for copper/low-k interconnect structures An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. E... | 08/05/2008 |
| 7405154 | Structure and method of forming electrodeposited contacts A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the diel... | 07/29/2008 |
| 7405152 | Reducing wire erosion during damascene processing A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby str... | 07/29/2008 |
| 7399699 | On-die reflectance arrangements Improved semiconductor reflectance arrangements (e.g., semiconductor devices, systems including semiconductor devices, methods, etc.). ... | 07/15/2008 |
| 7399649 | Semiconductor light-emitting device and fabrication method thereof An underlying layer ALY of GaN is formed on a sapphire substrate SSB; a transfer layer TLY of GaN with a bump and dip shaped surface is formed on the underlying layer ALY; a light absorption layer BLY is formed on the bump and dip shaped surface of the transfer laye... | 07/15/2008 |
| 7396768 | Copper damascene chemical mechanical polishing (CMP) for thin film head writer fabrication In one method and embodiment of the present invention, at least one coil layer is formed in a write head, using a two-slurry step of copper damascene chemical mechanical polishing method with a first slurry step removing the undesirable copper that is on top of the ... | 07/08/2008 |
| 7396760 | Method and system for reducing inter-layer capacitance in integrated circuits The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so ... | 07/08/2008 |
| 7397122 | Metal wiring for semiconductor device and method for forming the same A metal wiring for a semiconductor device and a method for forming the same are provided. The metal wiring includes a first insulating layer and a second insulating layer; an interlayer insulating film formed between the first and second insulating layers, wherein t... | 07/08/2008 |
| 7387963 | Semiconductor wafer and process for producing a semiconductor wafer A semiconductor wafer has an edge region with no defects larger than or equal to 0.3 μm. The wafers are produced by a process, comprising (a) providing a semiconductor wafer having a rounded and etched edge; (b) polishing the edge of the semiconductor wafer, in whi... | 06/17/2008 |
| 7384864 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ... | 06/10/2008 |
| 7384865 | Semiconductor device with a metal line and method of forming the same A method of forming a metal line in a semiconductor device includes: forming a lower insulation layer for insulation from the lower substrate; forming a first metal line at a certain region on the lower insulation layer; sequentially forming a first oxide layer, an ... | 06/10/2008 |
| 7381638 | Fabrication technique using sputter etch and vacuum transfer First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the... | 06/03/2008 |
| 7378348 | Polishing compound for insulating film for semiconductor integrated circuit and method for producing semiconductor integrated circuit An insulating film comprising an organic silicon material having a C—Si bond and a Si—O bond is used for a semiconductor integrated circuit, and for polishing of its surface, a polishing compound comprising water and particles of at least one specific rare earth... | 05/27/2008 |
| 7375023 | Method and apparatus for chemical mechanical polishing of semiconductor substrates Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material a... | 05/20/2008 |
| 7371629 | N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the n... | 05/13/2008 |
| 7368379 | Multi-layer interconnect structure for semiconductor devices An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers ... | 05/06/2008 |
| 7368389 | Methods of forming electrically conductive plugs A method of forming an electrically conductive plug includes providing an opening within electrically insulative material over a node location on a substrate. An electrically conductive material is formed within the opening and elevationally over the insulative mate... | 05/06/2008 |
