Did You Know...
...that Kleenex tissue was originally designed to be a gas mask filter? It was developed at the beginning of World War I to replace cotton, which was then in short supply as a surgical dressing.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8129267 | Alpha particle blocking wire structure and method fabricating same An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel ... | 03/06/2012 |
| 7977234 | Fabrication method of semiconductor integrated circuit device A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum p... | 07/12/2011 |
| 7816254 | Film forming method, fabrication process of semiconductor device, computer-readable recording medium and sputtering apparatus A film-forming method for forming a metal film on a substrate by a sputtering process includes the steps of depressurizing a processing space, in which deposition of the metal film is caused by the sputtering process, applying a DC bias voltage between the substrate... | 10/19/2010 |
| 7781329 | Reducing leakage in dielectric materials including metal regions including a metal cap layer in semiconductor devices By introducing an additional heat treatment prior to and/or after contacting a sensitive dielectric material with wet chemical agents, such as an electrolyte solution, enhanced performance with respect to leakage currents or dielectric strength may be accomplished d... | 08/24/2010 |
| 7718526 | Fabrication method of semiconductor integrated circuit device A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum p... | 05/18/2010 |
| 7678686 | Semiconductor device having copper metal line and method of forming the same A method of forming a copper metal line in a semiconductor device includes depositing an interlayer insulating layer on a semiconductor substrate having a lower metal line, forming a via contact hole and a metal line pattern in the semiconductor substrate, sequentia... | 03/16/2010 |
| 7674706 | System for modifying small structures using localized charge transfer mechanism to remove or deposit material A charge transfer mechanism is used to locally deposit or remove material for a small structure. A local electrochemical cell is created without having to immerse the entire work piece in a bath. The charge transfer mechanism can be used together with a charged part... | 03/09/2010 |
| 7666781 | Interconnect structures with improved electromigration resistance and methods for forming such interconnect structures Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielec... | 02/23/2010 |
| 7659195 | Method for forming metal line of semiconductor device A method for forming metal lines of a semiconductor device is disclosed. The metal line forming method includes forming plugs by perforating via-holes in an interlayer dielectric layer formed on a semiconductor substrate and burying a conductive material in the via-... | 02/09/2010 |
| 7638424 | Technique for non-destructive metal delamination monitoring in semiconductor devices By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor devic... | 12/29/2009 |
| 7569479 | Method for fabricating semiconductor device A method for fabricating a semiconductor device capable of preventing a device failure is provided. The method includes: forming an insulating layer with a contact hole on a semiconductor substrate; forming a seed layer on the contact hole through electroless platin... | 08/04/2009 |
| 7541279 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first met... | 06/02/2009 |
| 7504333 | Method of forming bit line of semiconductor device A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer.... | 03/17/2009 |
| 7446032 | Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films A process for enhancing the adhesion of directly plateable materials to an underlying dielectric is demonstrated, so as to withstand damascene processing. Using diffusion barriers onto which copper can be deposited facilitates conventional electrolytic processing. A... | 11/04/2008 |
| 7439179 | Healing detrimental bonds in deposited materials A method for healing detrimental bonds in deposited materials, for example porous, low-k dielectric materials, including oxydatively processing a deposited material, processing the deposited material with a trialkyl group III compound, and processing in the presence... | 10/21/2008 |
| 7422976 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ... | 09/09/2008 |
| 7416985 | Semiconductor device having a multilayer interconnection structure and fabrication method thereof A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall s... | 08/26/2008 |
| 7405152 | Reducing wire erosion during damascene processing A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby str... | 07/29/2008 |
| 7402513 | Method for forming interlayer insulation film It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprisi... | 07/22/2008 |
| 7396756 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ... | 07/08/2008 |
| 7396759 | Protection of Cu damascene interconnects by formation of a self-aligned buffer layer Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is pr... | 07/08/2008 |
| 7378340 | Method of manufacturing semiconductor device and semiconductor device The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film,... | 05/27/2008 |
| 7375022 | Method of manufacturing wiring board A method of manufacturing a wiring board is disclosed. The wiring board has: a capacitor, having multiple electrode layers which oppose each other with a dielectric layer in between, that is connected to a semiconductor chip; one or more via wirings which pierce the... | 05/20/2008 |
| 7368379 | Multi-layer interconnect structure for semiconductor devices An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers ... | 05/06/2008 |
| 7368324 | Method of manufacturing self-supporting contacting structures A self-supporting contacting structure is directly produced on a component that does not have a housing by applying a layer made of non conducting material and a layer made of an electrically conductive material to the component and to a support and by subsequently ... | 05/06/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7358170 | Methods of forming conductive interconnects, and methods of depositing nickel The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel sa... | 04/15/2008 |
| 7348672 | Interconnects with improved reliability An interconnect architecture with improved reliability. An interconnect with rounded top corners is inlaid in a dielectric layer. A filler borders the interconnect along the corners of the interconnect. ... | 03/25/2008 |
| 7341937 | Semiconductor device and method of manufacturing same Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on ... | 03/11/2008 |
| 7341909 | Methods of forming semiconductor constructions The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. ... | 03/11/2008 |
| 7338908 | Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that ... | 03/04/2008 |
| 7338884 | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a ... | 03/04/2008 |
| 7338899 | Method of forming contact plug in semiconductor device A method of forming a contact plug of a semiconductor device wherein, after a contact plug is formed in an interlayer insulation film, the interlayer insulation film is selectively etched so that the top surface of the contact plug is higher than the top surface of ... | 03/04/2008 |
| 7335991 | Pattern forming structure, pattern forming method, device, electro-optical device, and electronic apparatus There is provided a barrier structure provided with a concave portion corresponding to a pattern formed out of a functional liquid, the barrier structure comprising: a first concave portion provided in the barrier to correspond to a first pattern; and a second conca... | 02/26/2008 |
| 7332428 | Metal interconnect structure and method In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via is formed within the dielectric layer. A liner is formed over the dual damascene structure. The liner is... | 02/19/2008 |
| 7329953 | Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched... | 02/12/2008 |
| 7329607 | Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transforme... | 02/12/2008 |
| 7323409 | Method for forming a void free via A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via... | 01/29/2008 |
| 7319065 | Semiconductor component and method of manufacture A semiconductor component having a composite via structure with an enhanced aspect ratio and a method for manufacturing the semiconductor component. Vias having a first aspect ratio are formed in a contact layer disposed on a semiconductor substrate and filled with ... | 01/15/2008 |
| 7319238 | Semiconductor device and its manufacturing method An object of the present invention is to provide an active matrix type display unit having a pixel structure in which a pixel electrode formed in a pixel portion a scanning line (gate line) and a data line are suitably arranged, and high numerical aperture is realiz... | 01/15/2008 |
