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| Number | Title | Issue Date |
| 8178436 | Adhesion and electromigration performance at an interface between a dielectric and metal Interconnect structures having improved adhesion and electromigration performance and methods to fabricate thereof are described. A tensile capping layer is formed on a first conductive layer on a substrate. A compressive capping layer is formed on the tensile cappi... | 05/15/2012 |
| 8153518 | Method for fabricating metal interconnection of semiconductor device In a method for fabricating a metal interconnection of a semiconductor device, a lower interconnection and a lower insulation layer are formed over a semiconductor substrate. An etch stop layer is formed over the lower insulation layer. An upper insulation layer is ... | 04/10/2012 |
| 8110494 | Systems and methods for maximizing breakdown voltage in semiconductor devices Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while... | 02/07/2012 |
| 8026166 | Interconnect structures comprising capping layers with low dielectric constants and methods of making the same Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed abo... | 09/27/2011 |
| 8012871 | Semiconductor device and manufacturing method thereof A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A... | 09/06/2011 |
| 8003516 | BEOL interconnect structures and related fabrication methods Methods for forming voids in BEOL interconnect structures and BEOL interconnect structures. The methods include forming a temporary feature on a top surface of a first dielectric layer and depositing a second dielectric layer on the top surface of the first dielectr... | 08/23/2011 |
| 7981790 | Semiconductor device and method of fabricating the same There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and o... | 07/19/2011 |
| 7968450 | Methods for incorporating high dielectric materials for enhanced SRAM operation and structures produced thereby Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations... | 06/28/2011 |
| 7964495 | Method of manufacturing complementary metal oxide semiconductor image sensor A method of manufacturing a CMOS image sensor manufacturing includes forming a plurality of metal pads over a semiconductor substrate; electrically connecting the metal pads to lower conductive film patterns of multi-layer metal wires using metal contacts; depositin... | 06/21/2011 |
| 7897506 | Micro-electro-mechanical-system device with particles blocking function and method for making same The present invention discloses a MEMS device with particles blocking function, and a method for making the MEMS device. The MEMS device comprises: a substrate on which is formed a MEMS device region; and a particles blocking layer deposited on the substrate. ... | 03/01/2011 |
| 7897505 | Method for enhancing adhesion between layers in BEOL fabrication A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integ... | 03/01/2011 |
| 7871926 | Methods and systems for forming at least one dielectric layer A method for forming a structure includes forming at least one feature across a surface of a substrate. A nitrogen-containing dielectric layer is formed over the at least one feature. A first portion of the nitrogen-containing layer on at least one sidewall of the a... | 01/18/2011 |
| 7855141 | Semiconductor device having multiple wiring layers and method of producing the same A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches th... | 12/21/2010 |
| 7807566 | Method for forming dielectric SiOCH film having chemical stability A method for determining conditions for forming a dielectric SiOCH film, includes: (i) forming a dielectric SiOCH film on a substrate under conditions; (ii) evaluating the conditions using a ratio of Si—CH3 bonding strength to Si—O bonding strength of the film a... | 10/05/2010 |
| 7790603 | Integrated circuit insulators and related methods A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for forming an integrated circuit insulator. The method includes forming an insulating layer using a first stru... | 09/07/2010 |
| 7759244 | Method for fabricating an inductor structure or a dual damascene structure A method for fabricating an inductor structure or a dual damascene structure includes following steps. First, a dielectric layer is provided. Subsequently, a first etching process is performed on the dielectric layer so as to form a first opening in the dielectric l... | 07/20/2010 |
| 7749892 | Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated fil... | 07/06/2010 |
| 7732324 | Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the trans... | 06/08/2010 |
| 7718525 | Metal interconnect forming methods and IC chip including metal interconnect Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a cont... | 05/18/2010 |
| 7687392 | Semiconductor device having metal wiring and method for fabricating the same A method for fabricating a semiconductor device having a metal wiring is provided. The method includes: forming an inter-metal dielectric (IMD) layer on the semiconductor substrate having a first metal wiring formed therein, the IMD layer including a first IMD layer... | 03/30/2010 |
| 7678684 | Semiconductor integrated circuit device Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections ... | 03/16/2010 |
| 7678685 | Interposer and method for producing the same and electronic device An interposer includes a substrate made of an inorganic material; a through wiring including conductors embedded in through holes; and an upper wiring and (or) a lower wiring. The through wiring, the upper wiring and the lower wiring are respectively formed on preli... | 03/16/2010 |
| 7662713 | Semiconductor device production method that includes forming a gold interconnection layer A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a barrier layer provided between the first interconnection layer and the interleve... | 02/16/2010 |
| 7662712 | UV blocking and crack protecting passivation layer fabricating method A method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a patterned metal conductor layer. To provide UV blocking, an overlying separation layer is formed over the substrate, and a UV blocking layer of silicon enriched... | 02/16/2010 |
| 7651940 | Electronic part producing method and electronic part A conductor portion is formed on the surface of a support member. After the conductor portion is formed, a copper foil on which resin is attached is moved downward from above the conductor portion to pressurize the conductor portion while covering it. the copper foi... | 01/26/2010 |
| 7642185 | Insulating film forming method capable of enhancing adhesion of silicon carbide film, etc. and semiconductor device A first film made of silicon carbide is formed over a substrate. The surface of the first film is exposed to an oxidizing atmosphere to oxidize the surface layer of the first film. The surface of the first film is made in contact with chemical which makes the surfac... | 01/05/2010 |
| 7622380 | Method of improving adhesion between two dielectric films A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate layer with a low k insulating layer thereover. The low k insulating lay... | 11/24/2009 |
| 7611983 | Semiconductor device and a manufacturing method of the same A first BPSG film covering a transistor is formed. Next, a second BPSG film is formed on the first BPSG film. The B concentration in the first BPSG film is about five times higher than the B concentration in the second BPSG film. Next, the first BPSG film is separat... | 11/03/2009 |
| 7592250 | Multilayer wiring board, manufacturing method thereof, semiconductor device, and wireless electronic device A multilayer wiring board exhibiting excellent moldability and having a capacitor where variation of capacitance is suppressed, its producing method, a semiconductor device mounting a semiconductor chip on the multilayer wiring board, and a wireless electronic devic... | 09/22/2009 |
| 7589014 | Semiconductor device having multiple wiring layers and method of producing the same A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches th... | 09/15/2009 |
| 7572727 | Semiconductor formation method that utilizes multiple etch stop layers The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connection... | 08/11/2009 |
| 7572728 | Semiconductor device and method for manufacturing the same A semiconductor device and method with a dual damascene pattern uses buffer layers to prevent photoresist layer poisoning due to a reaction between an interlayer dielectric and a photoresist layer. Embodiments also relate to reducing the effects of plasma damage occ... | 08/11/2009 |
| 7569478 | Method and apparatus for manufacturing semiconductor device, control program and computer storage medium In a method for manufacturing a semiconductor device having a dual damascene structure, a semiconductor substrate formed by stacking a trench mask and a via hole resist mask on an insulating film is loaded into a processing chamber, and a via hole is formed by etchi... | 08/04/2009 |
| 7521355 | Integrated circuit insulators and related methods A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for forming an integrated circuit insulator. The method includes forming an insulating layer using a first stru... | 04/21/2009 |
| 7488680 | Conductive through via process for electronic device carriers Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form a... | 02/10/2009 |
| 7485569 | Printed circuit board including embedded chips and method of fabricating the same A printed circuit board having embedded chips, composed of a central layer having an embedded chip, an insulating layer formed on one surface or both surfaces of the central layer and having a via hole filled with conductive ink, and a circuit layer formed on the in... | 02/03/2009 |
| 7485570 | Silicon oxycarbide, growth method of silicon oxycarbide layer, semiconductor device and manufacture method for semiconductor device A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, te... | 02/03/2009 |
| 7482262 | Method of manufacturing semiconductor device Disclosed are embodiments relating to a method of manufacturing a semiconductor device that may improve the yield rate of the semiconductor device. In embodiments, the method may include preparing a substrate including a plurality of conductive patterns, forming fir... | 01/27/2009 |
| 7470611 | In situ deposition of a low K dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer de... | 12/30/2008 |
| 7462558 | Method for fabricating a circuit component A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a seco... | 12/09/2008 |
