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| Number | Title | Issue Date |
| 8183148 | Method of fabricating semiconductor device and semiconductor device A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the fi... | 05/22/2012 |
| 8178435 | High performance system-on-chip inductor using post passivation process A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer. | 05/15/2012 |
| 8173538 | Method of selectively forming a conductive barrier layer by ALD By providing a surface modification process prior to or during a self-limiting deposition process, the per se highly conformal deposition behavior may be selectively changed so as to obtain reliable coverage at specific surface areas, while significantly reducing or... | 05/08/2012 |
| 8173539 | Method for fabricating metal redistribution layer A method for fabricating a metal redistribution layer is described. A first opening and a second opening are formed in a dielectric layer over a first region and a second region thereof, respectively. A plurality of third openings are formed in the dielectric layer ... | 05/08/2012 |
| 8168529 | Forming seal ring in an integrated circuit die The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utili... | 05/01/2012 |
| 8168530 | Methods of forming one transistor DRAM devices A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body ... | 05/01/2012 |
| 8163646 | Interconnection wiring structure of a semiconductor device and method for manufacturing same A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper por... | 04/24/2012 |
| 8158509 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device is disclosed which comprises forming a gate structure on a major surface of a semiconductor substrate with a gate insulating film interposed therebetween, forming a first insulating film to cover top and side surfaces... | 04/17/2012 |
| 8143156 | Methods of forming high density semiconductor devices using recursive spacer technique High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of... | 03/27/2012 |
| 8129265 | High performance system-on-chip discrete components using post passivation process A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer. ... | 03/06/2012 |
| 8129266 | Method of forming a shielded semiconductor device and structure therefor In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of con... | 03/06/2012 |
| 8114767 | Structure, semiconductor structure and method of manufacturing a semiconductor structure and packaging thereof A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure com... | 02/14/2012 |
| 8103976 | Photo mask set for forming multi-layered interconnection lines and semiconductor device fabricated using the same A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and s... | 01/24/2012 |
| 8101516 | Method of forming contact hole pattern in semiconductor integrated circuit device A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film an... | 01/24/2012 |
| 8097535 | Fabrication of self-assembled nanowire-type interconnects on a semiconductor device The present invention relates to a semiconductor device with nanowire-type interconnect elements and a method for fabricating the same. The device comprises a metal structure with at least one self-assembled metal dendrite and forming an interconnect element (424... | 01/17/2012 |
| 8084353 | Methods for pitch reduction formation Methods and apparatus for providing a memory array fabrication process that concurrently forms memory array elements and peripheral circuitry. The invention relates to a method for fabricating memory arrays using a process that concurrently forms memory array elemen... | 12/27/2011 |
| 8084354 | Method of fabricating a metal cap layer with enhanced etch resistivity for copper-based metal regions in semiconductor devices During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via ope... | 12/27/2011 |
| 8080471 | MRAM cell structure Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by remo... | 12/20/2011 |
| 8076234 | Semiconductor device and method of fabricating the same including a conductive structure is formed through at least one dielectric layer after forming a via structure For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated ... | 12/13/2011 |
| 8067309 | Semiconductor device using metal nitride as insulating film and its manufacture method A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surfac... | 11/29/2011 |
| 8053353 | Method of making connections in a back-lit circuit A method for forming, on a surface of a thinned-down semiconductor substrate, a contact connected to a metal track of an interconnect stack formed on the opposite surface of the thinned-down substrate, including the steps of: forming, on the side of a first surface ... | 11/08/2011 |
| 8053354 | Reduced wafer warpage in semiconductors by stress engineering in the metallization system In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric materia... | 11/08/2011 |
| 8053352 | Method and mesh reference structures for implementing Z-axis cross-talk reduction through copper sputtering onto mesh reference planes A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-f... | 11/08/2011 |
| 8043957 | Semiconductor device, method for manufacturing semiconductor device and apparatus for manufacturing semiconductor The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a firs... | 10/25/2011 |
| 8043958 | Capping before barrier-removal IC fabrication method Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed... | 10/25/2011 |
| 8039387 | Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same includes forming a via pattern having a matrix form in a dielectric layer. The via pattern includes a via slit provided at the center of the via pattern and a plurality of via holes provided at an outer ... | 10/18/2011 |
| 8034707 | Method for fabricating semiconductor device and semiconductor device A method for fabricating a semiconductor device includes the steps of forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming a... | 10/11/2011 |
| 8034705 | Method of forming a seam-free tungsten plug A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top... | 10/11/2011 |
| 8034706 | Contact formation The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a particular thickness and having a portion of the trench positioned between two of a number of gates. This... | 10/11/2011 |
| 8034708 | Structure and process for the formation of TSVs An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into th... | 10/11/2011 |
| 8017516 | Method for stress free conductor removal A system and method for forming a planar dielectric layer includes identifying a non-planarity in the dielectric layer, forming one or more additional dielectric layers over the dielectric layer and planarizing at least one of the additional dielectric layers wherei... | 09/13/2011 |
| 8008185 | Semiconductor devices and methods of forming the same A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wid... | 08/30/2011 |
| 8003515 | Device and manufacturing method A description is given of a device, including a semiconductor chip, a first metal layer laterally extending over the semiconductor chip, the first metal layer having a first thickness. A dielectric layer laterally extends over the first metal layer, and a second met... | 08/23/2011 |
| 8003514 | Methods of fabricating semiconductor devices including storage node landing pads separated from bit line contact plugs A method can include forming gate lines on a semiconductor substrate and forming a first interlayer dielectric layer for insulating the gate lines from each other. First and second contact plugs are formed on the semiconductor substrate and landing pads are formed o... | 08/23/2011 |
| 8003513 | Multilayer circuit devices and manufacturing methods using electroplated sacrificial structures A multilayer circuit includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial... | 08/23/2011 |
| 7989338 | Grain boundary blocking for stress migration and electromigration improvement in CU interconnects Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodim... | 08/02/2011 |
| 7985674 | SiHsoak for low hydrogen SiN deposition to improve flash memory device performance Prior to deposition of a silicon nitride (SiN) layer on a structure, a non-plasma enhanced operation is undertaken wherein the structure is exposed to silane (SiH4) flow, reducing the overall exposure of the structure to hydrogen radicals. This results in... | 07/26/2011 |
| 7981789 | Feature patterning methods and structures thereof Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion o... | 07/19/2011 |
| 7977232 | Semiconductor wafer including cracking stopper structure and method of forming the same A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend over the device region and the dicing region. Multi-level interconnectio... | 07/12/2011 |
| 7977233 | Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1... | 07/12/2011 |
