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| Number | Title | Issue Date |
| 6743708 | Method of manufacturing semiconductor device including steps of forming groove and recess, and semiconductor device An interlayer insulation film (31) on a plug (11) is etched using a silicon nitride film (32) used in pattern etching of a bit line (12) as a hard mask such that the plug (11) projects into a groove (40). Another silicon nit... | 06/01/2004 |
| 6734094 | Method of forming an air gap within a structure by exposing an ultraviolet sensitive material to ultraviolet radiation An ultraviolet sensitive material may be formed within a semiconductor structure covered with a suitable hard mask. At an appropriate time, the underlying ultraviolet sensitive material may be exposed to ultraviolet radiation, causing the material to exhaust through... | 05/11/2004 |
| 6734095 | Method for producing cavities with submicrometer patterns in a semiconductor device using a freezing process liquid A method for producing cavities, which are patterned in submicrometer dimensions, in a cavity layer of a semiconductor device, is described. In the method, a process liquid is frozen in the trenches in a process layer which has been patterned by ribs and trenches, t... | 05/11/2004 |
| 6730571 | Method to form a cross network of air gaps within IMD layer In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches... | 05/04/2004 |
| 6724055 | Semiconductor structure having an interconnect and method of producing the semiconductor structure The semiconductor structure has an interconnect that is isolated by a cavity from an underlying insulating layer on a support. The fabrication method provides for the interconnect firstly to be patterned on a double layer and to be provided with an insulating coveri... | 04/20/2004 |
| 6720245 | Method of fabrication and device for electromagnetic-shielding structures in a damascene-based interconnect scheme A shielded interconnect and a method of manufacturing a shielded interconnect implemented in a damascene back-end-of-line technology to form electromagnetically shielded interconnects. The standard metallization of the damascene technology is used as a core layer in... | 04/13/2004 |
| 6720201 | MEMS device and fabrication method thereof A method for fabricating a MEMS device having a fixing part fixed to a substrate, a connecting part, a driving part, a driving electrode, and contact parts, includes patterning the driving electrode on the substrate; forming an insulation layer on the substrate; pat... | 04/13/2004 |
| 6713835 | Method for manufacturing a multi-level interconnect structure A method for forming interlevel dielectric layers in multilevel interconnect structures using air as the constituent low-k dielectric material that is compatible with damascene processes without introducing additional process steps. The conductive features character... | 03/30/2004 |
| 6713235 | Method for fabricating thin-film substrate and thin-film substrate fabricated by the method Supports (3) are formed to be arrayed on a support base (1), a sacrifice layer (15) is formed of a resin material, and the sacrifice layer (15) is planarized so as to expose the top of the respective supports (3), thereby forming a... | 03/30/2004 |
| 6709968 | Microelectronic device with package with conductive elements and associated method of manufacture A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and ... | 03/23/2004 |
| 6710449 | Interconnection structure and method for designing the same A wiring pattern has been enlarged by mutually different values, thereby forming two enlarged wiring patterns are formed. Then, regions where the two enlarged wiring patterns overlap each other are removed, thereby forming a dummy pattern. Alternatively, a simple-fi... | 03/23/2004 |
| 6709969 | Method for fabricating a gas insulated gate field effect transistor The present invention relates to a gas insulated gate field effect transistor and a fabricating method thereof which provides an improved insulator between the gate and the source-drain channel of a field effect transistor. The insulator is a vacuum or a gas filled ... | 03/23/2004 |
| 6706625 | Copper recess formation using chemical process for fabricating barrier cap for lines and vias A method of fabricating a planarized barrier cap layer over a metal structure comprising the following steps. A substrate having an opening formed therein is provided. The substrate having an upper surface. A planarized metal structure is formed within the opening. ... | 03/16/2004 |
| 6677225 | System and method for constraining totally released microcomponents A system and method are disclosed which constrain a microcomponent that is totally released from a substrate for handling of such totally released microcomponent. A preferred embodiment provides a system and method which constrain a totally released micro... | 01/13/2004 |
| 6660626 | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes an insulative base and a conductive trace. The conductive trace includes a pillar and a routing line. An electrolessly plated contact t... | 12/09/2003 |
| 6661068 | Semiconductor device and method of providing regions of low substrate capacitance A semiconductor structure (1), comprising a isolation region (5) formed on a semiconductor material (10). A pillar (15) is formed in the semiconductor material under the isolation region, where the pillar is capped with a first dielectric material (20) to... | 12/09/2003 |
| 6642138 | Process of making dual damascene structures using a sacrificial polymer A method is provided to deposit and pattern a sacrificial polymer, and form metal layers. A double hard mask is used to pattern and etch the sacrificial polymer. The double hard mask may be formed at temperatures below 400° C. The sacrificial polymer is ... | 11/04/2003 |
| 6635967 | Air gap semiconductor structure and method of manufacture An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first... | 10/21/2003 |
| 6627529 | Capacitance reduction by tunnel formation for use with semiconductor device A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A fir... | 09/30/2003 |
| 6607969 | Method for making pyroelectric, electro-optical and decoupling capacitors using thin film transfer and hydrogen ion splitting techniques A method for making a thin film device or pyroelectric sensor is provided. A film layer of thin film functional material is grown on a large diameter growth substrate. One or more protective layers may be deposited on the surface of the growth substrate b... | 08/19/2003 |
| 6605551 | Electrocoating process to form a dielectric layer in an organic substrate to reduce loop inductance Embodiments of the present invention include forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate, using an electrocoating process to reduce loop inductance between the co... | 08/12/2003 |
| 6599771 | Thermal infrared sensor and a method of manufacturing the same A thermal type infrared sensor and a method of manufacturing the same that have a high degree of freedom of structure and a low cost. An infrared ray detecting portion and a support leg are formed above flat plate-shape void formed inside of a semiconduct... | 07/29/2003 |
| 6596624 | Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier Disclosed is a multilayer integrated circuit structure joined to a chip carrier, and a process of making, in which the area normally occupied by a solid dielectric material in the IC is at least partially hollow. The hollow area can be filled with a gas, ... | 07/22/2003 |
| 6596611 | Method for forming wafer level package having serpentine-shaped electrode along scribe line and package formed A method for forming wafer level package that has a serpentine-shaped electrode formed along a scribe line in-between two adjacent IC dies and the package formed are disclosed. In the method, each of the I/O redistribution lines connecting from an I/O red... | 07/22/2003 |
| 6593214 | Method of manufacturing semiconductor device A photoresist is provided with an opening as a dummy pattern in a space area, i.e., a dummy region, other than a pattern of elements and circuits in one chip, thereby increasing the number of openings in the photoresist and performing ion implantation. Th... | 07/15/2003 |
| 6589861 | Method for fabricating a semiconductor device A method for fabricating a semiconductor device includes sequentially forming a stopping layer, an intermetal dielectric, and a capping layer on an interlayer dielectric, selectively removing the capping layer, the intermetal dielectric, and the stopping ... | 07/08/2003 |
| 6583044 | Buried channel in a substrate and method of making same A buried channel and a method of fabricating a buried channel in a substrate including depositing a layer of masking material onto a surface of a substrate, etching a groove in the masking layer, etching a channel into the substrate through the groove, an... | 06/24/2003 |
| 6576542 | Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry Conductive lines, such as co-axial lines, integrated circuitry incorporating such conductive lines, and methods of forming the same are described. In one aspect, a substrate having an outer surface is provided. A masking material is formed over the outer ... | 06/10/2003 |
| 6569779 | Device for gas sensing In order to obtain long time stability and usefulness for gas sensitive field-effect devices a micro structured surface is obtained below the final conducting layer. The conductive layer in the trenches or grooves will not only be protected to some extent... | 05/27/2003 |
| 6569702 | Triple layer isolation for silicon microstructure and structures formed using the same An isolation method for a single crystalline silicon microstructure using a triple layer structure is disclosed. The method includes forming the triple layer composed of an insulation layer formed over an exposed surface of the silicon microstructure, a c... | 05/27/2003 |
| 6562710 | Semiconductor device and method for fabricating the same After depositing a metal film on an insulating film on a semiconductor substrate, a first interlayer insulating film is formed on the metal film. After forming first plug openings in the first interlayer insulating film by etching the first interlayer ins... | 05/13/2003 |
| 6551924 | Post metalization chem-mech polishing dielectric etch A method for etching an insulating layer without damage to the conducting layer and associated liner layer within the insulating layer. A dielectric layer is deposited on a semiconductor substrate and then patterned. A liner layer and a conducting layer a... | 04/22/2003 |
| 6531332 | Surface micromachining using a thick release process A hybrid process combines a thin-film surface micromachining process such as by sputtering, evaporation or chemical vapor deposition with a thick-film surface micromachining and release process such as dry-film lamination. Such combination results in thin... | 03/11/2003 |
| 6531376 | Method of making a semiconductor device with a low permittivity region A method of making a semiconductor device (10) having a low permittivity region (24) includes forming a first layer (30/42) over a surface of a trench (20), and etching through an opening (70) in the first layer that is smaller than a width (W2) of the tr... | 03/11/2003 |
| 6524917 | Method for fabricating an integrated circuit with undercut etching The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a substrate (1) with an electrically insulating layer (2) above it; providing an interconnect (WL) having a lower conductive layer (3)... | 02/25/2003 |
| 6518165 | Method for manufacturing a semiconductor device having a metal layer floating over a substrate A method for manufacturing a semiconductor device where a passive element, such as, an inductor, is floating over a substrate, where an integrated circuit is formed, such that the overall area of the semiconductor device may be highly reduced. According t... | 02/11/2003 |
| 6511859 | IC-compatible parylene MEMS technology and its application in integrated sensors A combined IC/Mems process forms the IC parts first, and then forms the MEMS parts. One option forms a parylene overlayer, then forms a cavity under the parylene overlayer.... | 01/28/2003 |
| 6509623 | Microelectronic air-gap structures and methods of forming the same An improved microelectronic structure is disclosed. The improved structure includes an air-gap region formed by removing an insulating material through an aperture residing in a mask.... | 01/21/2003 |
| 6498070 | Air gap semiconductor structure and method of manufacture An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first... | 12/24/2002 |
| 6495445 | Semi-sacrificial diamond for air dielectric formation Disclosed is a structure and process for incorporating air or other gas as a permanent dielectric medium in a multilevel chip by providing CVD diamond as a semi-sacrificial interlevel and intralevel dielectric material. The semi-sacrificial dielectric is ... | 12/17/2002 |
