Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 8129264 | Method of fabricating a semiconductor device A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings ... | 03/06/2012 |
| 8084352 | Method of manufacturing semiconductor device A high-density N-type diffusion layer 116 formed in a separation area 115 makes it possible to reduce a collector current flowing through a parasitic NPN transistor 102. Thus, a normal CMOS process can be used to provide a driving circuit and a ... | 12/27/2011 |
| 8030202 | Temporary etchable liner for forming air gap An exemplary method lines the sidewalls of a first opening with a sacrificial material and then fills the first opening with a metallic conductor in a manner such that the metallic conductor contacts the substrate. Next, the method selectively removes the sacrificia... | 10/04/2011 |
| 8026165 | Process for producing air gaps in microstructures, especially of the air gap interconnect structure type for integrated circuits A process for producing at least one air gap in a microstructure, including supplying a microstructure having at least one gap filled with a sacrificial material that decomposes starting from a temperature θ1, this gap ... | 09/27/2011 |
| 7998855 | Solving via-misalignment issues in interconnect structures having air-gaps An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; and a metallization layer over the semiconductor substrate. The metallization layer includes a conductive line; a low-k dielectric region adjacent and h... | 08/16/2011 |
| 7994046 | Method for forming a dielectric layer with an air gap, and a structure including the dielectric layer with the air gap A method of forming a semiconductor structure includes providing a first dielectric layer with an opening above a substrate. An exposed surface portion of the first dielectric layer in the opening is transformed. A protective dielectric layer is formed along the tra... | 08/09/2011 |
| 7989337 | Implementing vertical airgap structures between chip metal layers A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited onto the first metal layer. A vertical air gap is etched from the first... | 08/02/2011 |
| 7960275 | Method for manufacturing an interconnection structure with cavities for an integrated circuit A method for manufacturing a structure of electrical interconnections for an integrated circuit having levels of interconnections, the method having steps of depositing a layer of sacrificial material on the substrate, etching the layer of sacrificial material with ... | 06/14/2011 |
| 7939446 | Process for reversing tone of patterns on integerated circuit and structural process for nanoscale fabrication A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a... | 05/10/2011 |
| 7932172 | Semiconductor chip and process for forming the same A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devic... | 04/26/2011 |
| 7910473 | Through-silicon via with air gap A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a liner... | 03/22/2011 |
| 7871922 | Methods for forming interconnect structures that include forming air gaps between conductive structures A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric... | 01/18/2011 |
| 7855139 | Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device are shown and described. In one embodiment, a method comprises providing a semiconductor substrate with a plurality of pillars formed thereon, depositin... | 12/21/2010 |
| 7842600 | Methods of forming interlayer dielectrics having air gaps Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A metal wire is formed in the trench such that the metal wire is recessed... | 11/30/2010 |
| 7811924 | Air gap formation and integration using a patterning cap Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer ... | 10/12/2010 |
| 7807563 | Method for manufacturing a layer arrangement and layer arrangement In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least o... | 10/05/2010 |
| 7807564 | Method and structure for low-k interlayer dielectric layer An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying the layer of transistor elements. An etch stop layer is formed overly... | 10/05/2010 |
| 7790601 | Forming interconnects with air gaps Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern i... | 09/07/2010 |
| 7741211 | Method for manufacturing a semiconductor device A semiconductor device can include a first interlayer dielectric layer disposed on a substrate, and an air gap defined in a portion of the first interlayer dielectric layer. The air gap can be formed within trenches etched into the first interlayer dielectric layer.... | 06/22/2010 |
| 7737020 | Method of fabricating CMOS devices using fluid-based dielectric materials Fluid-based dielectric material is used to backfill multiple patterned metal layers of an IC on a wafer. The patterned metal layers are fabricated using conventional CMOS techniques, and are IMD layers in particular embodiments. The dielectric material(s) are etched... | 06/15/2010 |
| 7732322 | Dielectric material with reduced dielectric constant and methods of manufacturing the same In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding regi... | 06/08/2010 |
| 7727878 | Method for forming passivation layer A method for forming a passivation layer is disclosed. In the method, a substrate containing a top surface and a bottom surface opposite to the top surface is first provided, wherein a plurality of conductive pads are disposed on the top surface thereof. Thereafter,... | 06/01/2010 |
| 7682963 | Air gap for interconnect application The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in ... | 03/23/2010 |
| 7648904 | Metal line in semiconductor device and method for forming the same A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches... | 01/19/2010 |
| 7645694 | Development or removal of block copolymer or PMMA-b-S-based resist using polar supercritical solvent Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the ... | 01/12/2010 |
| 7605073 | Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures Embodiments of the invention include apparatuses and methods relating to air gap interconnect structures having interconnects protected by a sealant. In various embodiments, the sealant includes alumina or silicon nitride. In some embodiments, the interconnect struc... | 10/20/2009 |
| 7601629 | Semiconductive device fabricated using subliming materials to form interlevel dielectrics The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over a semiconductive substrate, forming an interconnect structure [295, 297] within the ... | 10/13/2009 |
| 7575996 | Semiconductor device and method for manufacturing the same Embodiments relate to a semiconductor device and a method for manufacturing the same. Embodiments may include forming a lower porous oxide layer on a semiconductor substrate having a conductive layer, forming a pyrolytic polymer layer on the lower porous oxide layer... | 08/18/2009 |
| 7560375 | Gas dielectric structure forming methods Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrif... | 07/14/2009 |
| 7544602 | Method and structure for ultra narrow crack stop for multilevel semiconductor device An integrated circuit design and a method of fabrication and, more particularly, a semiconductor structure having an ultra narrow crack stop for use in multilevel level devices and a method of making the same. The structure includes a first dielectric layer having a... | 06/09/2009 |
| 7541277 | Stress relaxation, selective nitride phase removal A method for forming a dielectric cap layer over an interconnect layer formed by a back-end-of-the-line (BEOL) interconnect process, the interconnect process including: lithography, reactive ion etching (RIE), metal filling of BEOL conductors, and chemical-mechanica... | 06/02/2009 |
| 7531444 | Method to create air gaps using non-plasma processes to damage ILD materials A method of forming airgaps is provided where a blocking mask is applied to a substrate to shield a portion of the substrate from a beam of energy. After irradiation, the blocking mask is removed and a capping material is applied to the substrate. Alternatively, the... | 05/12/2009 |
| 7510959 | Method of manufacturing a semiconductor device having damascene structures with air gaps A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned dispos... | 03/31/2009 |
| 7507656 | Method and structure for low k interlayer dielectric layer An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying the layer of transistor elements. An etch stop layer is formed overly... | 03/24/2009 |
| 7485567 | Microelectronic circuit structure with layered low dielectric constant regions and method of forming same A method for manufacturing a microelectronic circuit includes the steps of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a plurality of alternating layers of layer dielectric ma... | 02/03/2009 |
| 7482261 | Interconnect structure for BEOL applications A semiconductor interconnect structure is provided that includes a new capping layer/dielectric material interface which is embedded inside the dielectric material. In particular, the new interface is an air gap that is located in the upper surface of a dielectric m... | 01/27/2009 |
| 7459389 | Method of forming a semiconductor device having air gaps and the structure so formed A method of forming a semiconductor device. Depositing alternating layers of a first and a second dielectric material, wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature within the alternating layer... | 12/02/2008 |
| 7449407 | Air gap for dual damascene applications An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus... | 11/11/2008 |
| 7439172 | Circuit structure with low dielectric constant regions and method of forming same A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a pluralit... | 10/21/2008 |
| 7422940 | Layer arrangement A process for producing a layer arrangement, in which a plurality of electrically conductive structures are formed on a substrate, a first electrically insulating layer is formed on the plurality of electrically conductive structures, in such a manner than trenches ... | 09/09/2008 |
