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| Number | Title | Issue Date |
| 8187967 | Method of manufacturing a non-volatile memory device A method of manufacturing a non-volatile memory device providing a semiconductor layer in which a cell region and a peripheral region are defined, sequentially forming a first insulating layer, a first conductive layer, a second insulating layer, and a second conduc... | 05/29/2012 |
| 8187968 | Methods of post-contact back end of line through-hole via integration Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integ... | 05/29/2012 |
| 8187966 | Manufacturing method for semiconductor integrated circuit device A Cu-CMP step applied to processes for 130 nm, 90 nm, and 65 nm technical nodes or the like mainly employs slurry to which an anticorrosive agent is added for preventing corrosion of Cu wiring. The inventors of the present application have studied and clearly found ... | 05/29/2012 |
| 8183146 | Manufacturing method for a buried circuit structure A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (... | 05/22/2012 |
| 8183145 | Structure and methods of forming contact structures Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the ... | 05/22/2012 |
| 8173537 | Methods for reducing UV and dielectric diffusion barrier interaction Stability of an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer is critical for successful integration. UV-resistant diffusion barrier layers are formed by depositing the layer in a hydrogen-... | 05/08/2012 |
| 8168528 | Restoration method using metal for better CD controllability and Cu filing Methods of making interconnect structures are provided. In one aspect of the innovation, when forming a trench or via in a dielectric layer, the sidewall surface of another via and/or trench is covered with a metal oxide layer. The metal oxide layer can prevent and/... | 05/01/2012 |
| 8163645 | Method for providing a redistribution metal layer in an integrated circuit A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation i... | 04/24/2012 |
| 8138083 | Interconnect structure having enhanced electromigration reliability and a method of fabricating same An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal intercon... | 03/20/2012 |
| 8138082 | Method for forming metal interconnects in a dielectric material A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of ... | 03/20/2012 |
| 8124522 | Reducing UV and dielectric diffusion barrier interaction through the modulation of optical properties Provided are methods of stabilizing an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer. Methods include modulating the optical properties reduces the effects of UV radiation on the dielectric... | 02/28/2012 |
| 8124521 | Electrical through contact A method of fabricating an electrical contact through a through hole in a substrate, wherein the through hole is at least in part filled with a liquid conductive material and the solidified liquid conductive material provides an electrical contact through the throug... | 02/28/2012 |
| 8114766 | Method for manufacturing semiconductor device Method of manufacturing a semiconductor device, which achieves a reduction in manufacturing cost and prevents, a damage on the interconnect layer by an influence of the etchant solution, since the support substrate can be easily stripped from the interconnect layer.... | 02/14/2012 |
| 8110493 | Pulsed PECVD method for modulating hydrogen content in hard mask A method for forming a PECVD deposited amorphous carbon or ashable hard mask (AHM) in a trench or a via with less than 30% H content at a process temperature below 500° C., e.g., about 400° C. produces low H content hard masks with high selectivity and little or n... | 02/07/2012 |
| 8105936 | Methods for forming dielectric interconnect structures Solutions for forming dielectric interconnect structures are provided. Specifically, the present invention provides methods of forming a dielectric interconnect structure having a noble metal layer that is formed directly on a modified dielectric surface. In a typic... | 01/31/2012 |
| 8105935 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a s... | 01/31/2012 |
| 8097534 | Method for manufacturing semiconductor device and storage medium On an etching target film formed on a substrate, a three-layer resist is laminated. This three-layer resist includes an organic film and a resist film developed into a resist pattern. Through the resist pattern, the organic film is etched into a mask pattern through... | 01/17/2012 |
| 8093149 | Semiconductor wafer and manufacturing method for semiconductor device A semiconductor wafer and a manufacturing method for a semiconductor device are provided, which prevent peeling-off of films and pattern skipping in a wafer edge portion. A silicone substrate has formed thereon gate structures in active regions isolated by a trench ... | 01/10/2012 |
| 8088685 | Integration of bottom-up metal film deposition The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of ... | 01/03/2012 |
| 8084350 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes can prevent defects of a semiconductor device due to the deterioration of electro migration (EM)/stress migration (SM) properties of the device as a result of metal corrosion and void generation in burying a... | 12/27/2011 |
| 8084351 | Contact structure of a semiconductor device A method for fabricating a contact of a semiconductor device includes the steps of forming a dielectric layer having a contact hole on a semiconductor substrate, forming an out-gassing barrier layer comprising a poly-silicon layer to cover at least inner walls of th... | 12/27/2011 |
| 8080470 | Wiring structure and semiconductor device, and their fabrication methods A fabrication method for a wiring structure of the present invention includes: a process of forming a conductive wiring layer; a process of forming a wiring pattern on the wiring layer; a process of forming an insulative wiring interlayer film between wires of the w... | 12/20/2011 |
| 8067308 | Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support A semiconductor device has a conductive via formed through in a first side of the substrate. A first interconnect structure is formed over the first side of the substrate. A semiconductor die or component is mounted to the first interconnect structure. An encapsulan... | 11/29/2011 |
| 8048794 | 3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport A method of fabricating a thin wafer die includes creating circuits and front-end-of-line wiring on a silicon wafer, drilling holes in a topside of the wafer, depositing an insulator on the drilled holes surface to provide a dielectric insulator, removing any excess... | 11/01/2011 |
| 8048796 | Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material In a sophisticated metallization system of a semiconductor device, air gaps may be formed in a self-aligned manner on the basis of a sacrificial material, such as a carbon material, which is deposited after the patterning of a dielectric material for forming therein... | 11/01/2011 |
| 8048795 | Self-assembly pattern for semiconductor integrated circuit A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer l... | 11/01/2011 |
| 8039386 | Method for forming a through silicon via (TSV) A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portio... | 10/18/2011 |
| 8026164 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device, includes steps of forming an organic insulating film over a semiconductor substrate, irradiating an electron beam to a surface of the organic insulating film, forming recesses in the organic insulating film, forming ... | 09/27/2011 |
| 8021974 | Structure and method for back end of the line integration An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the co... | 09/20/2011 |
| 8012870 | Wiring structure between steps and wiring method thereof In a wiring structure between steps in which a step portion is covered by an insulating slope formed by providing and drying droplets of an insulating ink in which an insulating material is dispersed in a dispersion medium and a wiring line formed by drying and firi... | 09/06/2011 |
| 8008184 | Semiconductor device manufacturing method, semiconductor manufacturing apparatus and storage medium A seed layer is formed on a surface of an insulating film and along a recess of the insulating film, and after a copper wiring is buried in the recess, a barrier film is formed, and an excessive metal is removed from the wiring. On a surface of a copper lower layer ... | 08/30/2011 |
| 7998854 | Wafer level integration module with interconnects A method and apparatus for manufacturing an integrated circuit (IC) device (90) is disclosed. A wafer (10) is first provided having a first or top surface and a second or bottom surface. The wafer may be a blank polished or unpolished silicon wafer or ... | 08/16/2011 |
| 7998853 | Semiconductor device with through substrate vias Methods for making and testing a semiconductor device with through substrate vias are described. In some examples, a method of making a semiconductor device includes: forming through substrate vias (TSVs) in a substrate having an integrated circuit (IC) die, the sub... | 08/16/2011 |
| 7989336 | Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill... | 08/02/2011 |
| 7985673 | Semiconductor device for low-power applications and a method of manufacturing thereof The invention relates to a semiconductor device manufactured in a process technology, the semiconductor device having at least one wire located in an interconnect layer of said semiconductor device, the at least one wire having a wire width (W) and a wire thickness ... | 07/26/2011 |
| 7972954 | Porous silicon dielectric Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A manufacturing method comprises forming a layer of silicon over a substrate, forming an opening through the layer of silicon, filling the opening w... | 07/05/2011 |
| 7972955 | Three dimensional semiconductor memory device and method of fabricating the same Provided are a three dimensional semiconductor memory device and a method of fabricating the same. The method includes forming a stepwise structure by using mask patterns and a sacrificial mask pattern formed on the mask patterns as a consumable etch mask. ... | 07/05/2011 |
| 7968447 | Semiconductor device and methods of manufacturing the same A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections ... | 06/28/2011 |
| 7964493 | Method of manufacturing semiconductor device A metal layer is formed on an upper surface of a resin layer provided to cover a plurality of semiconductor chips at a side on which an internal connecting terminal is disposed and the internal connecting terminal, and the metal layer is pressed to cause the metal l... | 06/21/2011 |
| 7964494 | Integrated connection arrangements A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer.... | 06/21/2011 |
