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| Number | Title | Issue Date |
| 8187964 | Integrated circuit device and method An integrated circuit device includes a semiconductor chip with a metallization layer on the chip. A gas-phase deposited insulation layer is disposed on the metallization layer. ... | 05/29/2012 |
| RE43404 | Methods for providing void-free layer for semiconductor assemblies A method of providing a substantially void free layer for one or more flip chip assemblies, or one or more microelectronic components, utilizing a curable encapsulant. Also disclosed is a method of injecting an encapsulant into an assembly and a method of treating a... | 05/22/2012 |
| 8183142 | Semiconductor device and a method of manufacturing the same A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an openin... | 05/22/2012 |
| 8173536 | Semiconductor device and method of forming column interconnect structure to reduce wafer stress An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photor... | 05/08/2012 |
| 8168525 | Electronic part mounting board and method of mounting the same An electronic part mounting board includes an insulating board, a pad formed on the insulating board, a bump formed on the pad, and a film having heat resistance and electrical insulating properties and formed on the insulating board except the pad and the bump. A m... | 05/01/2012 |
| 8163642 | Package substrate with dual material build-up layers Multi-layered, organic build-up semiconductor package substrates have build-up layers with layers of both fibrous organic dielectric material and non-fibrous organic dielectric material. Non-fibrous dielectric material layers are positioned below the signal metal la... | 04/24/2012 |
| 8163643 | Enhanced pad design for solder attach devices A semiconductor device is disclosed that has a die and a substrate having a die attachment area with a perimeter. A layer of solder connects the substrate and the die, the solder layer having at least one vent channel connected to the perimeter of the die attachment... | 04/24/2012 |
| 8153516 | Method of ball grid array package construction with raised solder ball pads The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductiv... | 04/10/2012 |
| 8148253 | Electronic component soldering structure and electronic component soldering method In an electronic component soldering method of connecting a terminal provided on a flexible substrate to an electrode of a rigid substrate, after solder-mixed resin in which solder particles are mixed in thermosetting resin has been applied onto the rigid substrate ... | 04/03/2012 |
| 8148254 | Method of manufacturing semiconductor device There is provided a method of manufacturing a semiconductor device. The method includes the successive steps of: (a) providing a semiconductor substrate; (b) forming a plurality of semiconductor chips having electrode pads on the semiconductor substrate; (c) forming... | 04/03/2012 |
| 8138078 | Mechanically stable diffusion barrier stack and method for fabricating the same A mechanically stable diffusion barrier stack structure and method of fabricating the same is disclosed. The diffusion barrier stack structure having a molybdenum nitride layer deposited on a molybdenum layer and operates to prevent diffusion between a semiconductor... | 03/20/2012 |
| 8133808 | Wafer level chip package and a method of fabricating thereof Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies. ... | 03/13/2012 |
| 8124519 | Apparatus and method for bonding silicon wafer to conductive substrate A system and method is disclosed for bonding a substrate to a semiconductor die that is prone to curling when subjected to an elevated temperature in a solder reflow oven, for example, thereby improving the electrical and mechanical bonding for large dies, wafers, c... | 02/28/2012 |
| 8119515 | Bonding pad for anti-peeling property and method for fabricating the same A bonding pad includes a conductive layer formed over an insulation layer, and a dummy pattern penetrating the insulation layer and stuck in the conductive layer, wherein a bonding process is performed. ... | 02/21/2012 |
| 8105932 | Mixed wire semiconductor lead frame package One embodiment includes an encapsulated semiconductor package having a lead frame with die pad surrounded by a plurality of first and second leadfingers. A semiconductor chip including chip contact pads on its upper active surface is attached to the die pad. A plura... | 01/31/2012 |
| 8105933 | Localized alloying for improved bond reliability In some embodiments a method of forming a gold-aluminum electrical interconnect is described. The method may include interposing a diffusion retardant layer between the gold and the aluminum (1002), the diffusion retardant layer including regions containing a... | 01/31/2012 |
| 8084349 | Method for forming post bump Disclosed is a method for forming post bumps, the method including the steps of: forming a seed layer for metal plating on a substrate; forming a resist layer having openings provided as positions where the seed layer is subjected to metal plating; forming a dummy s... | 12/27/2011 |
| 8084348 | Contact pads for silicon chip packages A method for manufacturing a silicon chip package for a circuit board assembly provides a package with a silicon chip and an array of first contact pads that are provided by a first conductive material. A plurality of second contact pads are provided from a gold mat... | 12/27/2011 |
| 8076232 | Semiconductor device and method of forming composite bump-on-lead interconnection A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The inte... | 12/13/2011 |
| 8067306 | Integrated circuit packaging system with exposed conductor and method of manufacture thereof A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a component connector on the substrate; forming a resist layer on the substrate with the component connector exposed; forming a vertical insertion cavity in th... | 11/29/2011 |
| 8062968 | Interposer for redistributing signals A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through ... | 11/22/2011 |
| 8062969 | Methods of selectively growing nickel-containing materials The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel sa... | 11/22/2011 |
| 8058163 | Enhanced reliability for semiconductor devices using dielectric encasement A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The ... | 11/15/2011 |
| 8048793 | Flip chip for electrical function test and manufacturing method thereof Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photore... | 11/01/2011 |
| 8039384 | Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved by forming different height first and second conductive layer above a substrate. A first patterned photoresist layer is formed over the substrate. A first cond... | 10/18/2011 |
| 8034703 | Semiconductor device and method for manufacturing the same In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant... | 10/11/2011 |
| 8030200 | Method for fabricating a semiconductor package A method for fabricating a semiconductor package, includes the steps of forming a first terminal at a first substrate; mixing a polymer resin and solder particles to provide a mixture; covering at least one of an upper surface and side surfaces of the first terminal... | 10/04/2011 |
| 8017515 | Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief A semiconductor device has a first conductive layer formed over a top surface of a substrate. A first insulating layer is formed over the substrate. A first dielectric layer is formed over the first insulating layer. A second conductive layer is formed over the firs... | 09/13/2011 |
| 8003512 | Structure of UBM and solder bumps and methods of fabrication Methods and UBM structures having bilayer or trilayer UBM layers that include a thin TiW adhesion layer and a thick Ni-based barrier layer thereover both deposited under sputtering operating conditions that provide the resultant bilayer or trilayer UBM layers with m... | 08/23/2011 |
| 7998852 | Methods for forming an RF device with trench under bond pad feature Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance o... | 08/16/2011 |
| 7994045 | Bumped chip package fabrication method and structure A method of fabricating a bumped chip package includes forming a first seed layer on a dielectric layer, the dielectric layer comprising a dielectric layer opening exposing a substrate terminal of a substrate, the first seed layer being formed within the dielectric ... | 08/09/2011 |
| 7994043 | Lead free alloy bump structure and fabrication method A method includes forming a patterned resist layer comprising a resist layer opening overlying a bond pad of a substrate. The resist layer opening is at least partially filled with a first solder component layer. A second solder component layer is formed on the firs... | 08/09/2011 |
| 7994044 | Semiconductor chip with contoured solder structure opening Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first dielectric layer over a first conductor structure of a semiconductor chip ... | 08/09/2011 |
| 7977231 | Die bonder incorporating dual-head dispenser Adhesive is dispensed for conducting die bonding onto a substrate including rows of bond pads aligned along a first axis and columns of bond pads aligned along a second axis transverse to the first axis where target dispensing positions are located. A first dispensi... | 07/12/2011 |
| 7972953 | Pad structure for liquid crystal display and method of manufacturing thereof A liquid crystal display has a pad structure. The pad structure includes at least one pad formed on a substrate, an insulating film formed on the pad, and at least one conductive layer connected to the pad through contact holes defined through the insulating film. T... | 07/05/2011 |
| 7964492 | Semiconductor device and automotive AC generator A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material and a lead electrode bonded to a second surface of the semiconductor element supported on the support membe... | 06/21/2011 |
| 7960271 | Semiconductor device and method of manufacturing the same The present invention provides a semiconductor device that can suppresses poor connection caused by the variation of the heights of bumps during reflow heating, can be applied to a narrow array pitch, and can freely adjust the heights of the bumps. ... | 06/14/2011 |
| 7960270 | Method for fabricating circuit component A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylind... | 06/14/2011 |
| 7935622 | Support with solder ball elements and a method for populating substrates with solder balls A support with solder ball elements for loading substrates with ball contacts is disclosed. One embodiment provides a system for loading substrates with ball contacts and a method for loading substrates with ball contacts. The support has a layer of adhesive applied... | 05/03/2011 |
| 7932169 | Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with ... | 04/26/2011 |
