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| Number | Title | Issue Date |
| 8394712 | Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that s... | 03/12/2013 |
| 8361896 | Signal transmission for high speed interconnections A connector assembly includes a substrate and a connector. The substrate includes a ground layer and a trace layer. The substrate defines a substrate edge, and the ground layer defines a ground edge. The connector is mounted on the substrate such that a portion of t... | 01/29/2013 |
| 8273650 | Method of fabricating thin film interface for internal light reflection and impurities isolation A high-quality epitaxial silicon thin layer is formed on an upgraded metallurgical grade silicon (UMG-Si) substrate. A thin film interface is fabricated between the UMG-Si substrate and the epitaxial silicon thin layer. The interface is capable of internal light ref... | 09/25/2012 |
| 8232191 | Semiconductor device manufacturing method A method of manufacturing a semiconductor device including forming a gate insulating film and a gate electrode over a Si substrate; forming a recess in the Si substrate at both sides of the gate electrode; forming a first Si layer including Ge in the recess; forming... | 07/31/2012 |
| 8202795 | Method of fabricating a semiconductor device having a plug A method of fabricating a semiconductor device, the method includes forming gate patterns on a substrate, recessing the substrate between the gate patterns, thereby forming a first resulting structure including recesses, forming a gate spacer layer on an entire surf... | 06/19/2012 |
| 8173535 | Wafer structure to reduce dark current A wafer structure for an image sensor includes a substrate that has a given conductivity type, a given dopant concentration, and a given concentration of oxygen. An intermediate epitaxial layer is formed over the substrate. The intermediate epitaxial layer has the s... | 05/08/2012 |
| 8124518 | Semiconductor heterostructure nanowire devices Nanowire devices comprising core-shell or segmented nanowires are provided. In these nanowire devices, strain can be used as a tool to form metallic portions in nanowires made from compound semiconductor materials, and/or to create nanowires in which embedded quantu... | 02/28/2012 |
| 7998851 | Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug an... | 08/16/2011 |
| 7964491 | Method of forming metal wiring of nonvolatile memory device A method of forming metal wirings of a nonvolatile memory device include forming a first insulating layer over a semiconductor substrate including a first junction area and a second junction area, forming first and second contact holes through which the first and se... | 06/21/2011 |
| 7790593 | Method for tuning epitaxial growth by interfacial doping and structure including same A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that r... | 09/07/2010 |
| 7605070 | Semiconductor device having contact plug formed in double structure by using epitaxial stack and metal layer and method for fabricating the same Disclosed are a contact plug of a semiconductor device and a method for fabricating the same. The semiconductor device includes: an epitaxial stack formed by inserting a heteroepitaxy layer between a pair of homoepitaxy layers; and a contact plug including a metal l... | 10/20/2009 |
| 7485560 | Method for fabricating crystalline silicon thin films An amorphous silicon (Si) film is taken to form a metal silicide of Si—Al(aluminum) under a high temperature. Al atoms is diffused into the amorphous Si film for forming the metal silicide of Si—Al as nucleus site. Then through heating and annealing, a microcrys... | 02/03/2009 |
| 7439142 | Methods to fabricate MOSFET devices using a selective deposition process In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsi... | 10/21/2008 |
| 7430731 | Method for electrochemically fabricating three-dimensional structures including pseudo-rasterization of data Some embodiments of the invention are directed to techniques for electrochemically fabricating multi-layer three-dimensional structures where selective patterning of at least one or more layers occurs via a mask which is formed using data representing cross-sections... | 09/30/2008 |
| 7425500 | Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors A method for fabricating a three-dimensional transistor is described. Atomic Layer Deposition of nickel, in one embodiment, is used to form a uniform silicide on all epitaxially grown source and drain regions, including those facing downwardly. ... | 09/16/2008 |
| 7405142 | Semiconductor substrate and field-effect transistor, and manufacturing method for same A semiconductor substrate manufacturing method has a first layer formation process, a second layer formation process, a heat treatment process, and a polishing process; in the first layer formation process, the thickness of the first SiGe layer is set to less than t... | 07/29/2008 |
| 7399693 | Semiconductor film manufacturing method and substrate manufacturing method This invention provides a semiconductor film manufacturing method using a new separation technique and applications thereof. The semiconductor film manufacturing method of this invention includes a separation layer forming a step of hetero-epitaxially growing a sepa... | 07/15/2008 |
| 7393763 | Manufacturing method of monocrystalline gallium nitride localized substrate There is provided a monocrystalline gallium nitride localized substrate suitable for manufacturing electronic-optical united devices in which electronic devices and optical devices are mixedly mounted on the same silicon substrate. An area in which monocrysta... | 07/01/2008 |
| 7381623 | Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second ga... | 06/03/2008 |
| 7375019 | Image sensor and method for fabricating the same An image sensor and a method for fabricating the same are disclosed, to improve a contact quality between a contact plug and a source diffusion layer. The image sensor includes a photodiode in an active area of a semiconductor substrate, for receiving incident exter... | 05/20/2008 |
| 7361563 | Methods of fabricating a semiconductor device using a selective epitaxial growth technique Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are... | 04/22/2008 |
| 7355254 | Pinning layer for low resistivity N-type source drain ohmic contacts A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region; and a pinning layer disposed between the source region and the first... | 04/08/2008 |
| 7342275 | Semiconductor device and method of manufacturing the same Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact... | 03/11/2008 |
| 7338874 | Highly integrated semiconductor device with silicide layer that secures contact margin and method of manufacturing the same Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a... | 03/04/2008 |
| 7329596 | Method for tuning epitaxial growth by interfacial doping and structure including same A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that r... | 02/12/2008 |
| 7326989 | Thin film capacitor and its manufacture method A thin film capacitor is provided which includes a single crystal high dielectric constant dielectric layer. The thin film capacitor has a single crystal silicon substrate, a single crystal intermediate layer epitaxially grown on the single crystal silicon substrate... | 02/05/2008 |
| 7312154 | Method of polishing a semiconductor-on-insulator structure A method of polishing a semiconductor layer formed on a transparent substrate is described, the method including measuring the thickness of the semiconductor from the substrate side of the semiconductor layer simultaneously with the polishing, and using the thicknes... | 12/25/2007 |
| 7300837 | FinFET transistor device on SOI and method of fabrication A FinFET transistor on SOI device and method of fabrication is provided. At least two FinFET fins each having an upper poly-silicate glass portion and a lower silicon portion are formed using spacer patterning technology. Each fin is formed on a sacrificial SiN mask... | 11/27/2007 |
| 7279047 | Reactor for extended duration growth of gallium containing single crystals An apparatus for growing bulk GaN and AlGaN single crystal boules, preferably using a modified HVPE process, is provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If de... | 10/09/2007 |
| 7256075 | Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer The invention relates to a method of transferring useful layers from a donor wafer which includes a multi-layer structure on the surface of the donor wafer that has a thickness sufficient to form multiple useful layers for subsequent detachment. The layers may be fo... | 08/14/2007 |
| 7250356 | Method for forming metal silicide regions in an integrated circuit A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heate... | 07/31/2007 |
| 7250359 | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer.... | 07/31/2007 |
| 7250360 | Single step, high temperature nucleation process for a lattice mismatched substrate A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V rea... | 07/31/2007 |
| 7247528 | Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconducto... | 07/24/2007 |
| 7247551 | Substrate for electronic device, method for manufacturing substrate for electronic device, and electronic device The invention provides a substrate for an electronic device including a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation and which contains a metal oxide having a perovskite str... | 07/24/2007 |
| 7238580 | Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant ... | 07/03/2007 |
| 7235486 | Method for forming tungsten materials during vapor deposition processes In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to a first re... | 06/26/2007 |
| 7223662 | Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number o... | 05/29/2007 |
| 7220673 | Method for depositing tungsten-containing layers by vapor deposition techniques In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes forming a tungsten nucleation layer by sequentially exposing a substrate to a boron-containing gas and a tungsten-containing gas within a processing cham... | 05/22/2007 |
| 7214584 | Method for forming semiconductor device capable of preventing bunker defect Disclosed is a method for preventing a bunker defect generation on a lower portion of a cylinder type metal bottom electrode. The method includes the steps of: forming an etch stop layer on a bottom structure with a conductive region and an insulation region; formin... | 05/08/2007 |
