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| Number | Title | Issue Date |
| 8071469 | Semiconductor device and method of fabricating the same A semiconductor device having increased reliability includes a fuse region and a monitoring region. Fuses are located on an insulation film in the fuse region and are exposed through fuse windows. A monitoring pattern is located on the insulation film in the monitor... | 12/06/2011 |
| 7977230 | Rectangular contact used as a low voltage fuse element A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contac... | 07/12/2011 |
| 7863177 | Fuse in a semiconductor device and method for fabricating the same The present invention relates to a fuse in a semiconductor device and method for fabricating the same. An oxide film is formed on sidewalls of a barrier metal layer in a bottom portion of a fuse pattern, thereby preventing the barrier metal layer from being exposed.... | 01/04/2011 |
| 7816246 | Methods of making semiconductor fuses Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabri... | 10/19/2010 |
| 7682958 | Method for producing an integrated circuit including a fuse element, a fuse-memory element or a resistor element A method for producing an integrated circuit including a fuse element, a fuse-memory element or a resistor element is disclosed. In one embodiment, at least one metallization layer is applied onto a substrate. A hard mask is applied onto the at least one metallizati... | 03/23/2010 |
| 7682957 | Method of forming pad and fuse in semiconductor device A method of forming a pad and a fuse in a semiconductor device. A copper layer located in both a fuse region and a pad region is formed in a dielectric layer. A first insulating layer is formed on the dielectric layer to cover the copper layer and selectively etched... | 03/23/2010 |
| 7632748 | Semiconductor device having a fuse barrier pattern and fabrication method thereof In a semiconductor device having a plurality of fuses and a method of fabricating the same, the semiconductor device comprises an inter-layer dielectric layer on a semiconductor substrate; a plurality of fuses on the inter-layer dielectric layer, an inter-metallic d... | 12/15/2009 |
| 7579266 | Fuse structure for semiconductor integrated circuit with improved insulation film thickness uniformity and moisture resistance When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even a... | 08/25/2009 |
| 7572724 | Doped single crystal silicon silicided eFuse An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon laye... | 08/11/2009 |
| 7479447 | Method of forming a crack stop void in a low-k dielectric layer between adjacent fuses A crack stop void is formed in a low-k dielectric layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The crack stop void is formed simultaneously with the formation of an int... | 01/20/2009 |
| 7442626 | Rectangular contact used as a low voltage fuse element A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contac... | 10/28/2008 |
| 7439623 | Semiconductor device having via connecting between interconnects A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed... | 10/21/2008 |
| 7439102 | Semiconductor fuse box and method for fabricating the same A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include ... | 10/21/2008 |
| 7425472 | Semiconductor fuses and semiconductor devices containing the same A fuse for use in a semiconductor device includes spaced-apart terminals with at least two layers of conductive material and a single-layer conductive link joining the spaced-apart terminals and including a single layer of conductive material. A first, lower layer o... | 09/16/2008 |
| 7422972 | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the ... | 09/09/2008 |
| 7413936 | Method of forming copper layers A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the centr... | 08/19/2008 |
| 7402464 | Fuse box of semiconductor device and fabrication method thereof A fuse box includes a semiconductor substrate having a fuse region, and a lower line in the fuse region that has a first region and a second region. An upper line is placed on the upper part of the lower line to overlap the first region. A fuse is placed on the uppe... | 07/22/2008 |
| 7397106 | Laser fuse with efficient heat dissipation A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structu... | 07/08/2008 |
| 7369947 | Quantification of adsorbed molecular contaminant using thin film measurement A test method for measuring adsorbed molecular contamination uses a test structure that includes a substrate comprising a plurality of separated test sites having a plurality separate thicknesses having a base design thickness and a designed thickness interrelations... | 05/06/2008 |
| 7368380 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device is disclosed in which a metallic deposit is stably formed on the anode side with small variation in film thickness, and plating is prevented on the cathode side without carrying out any additional processing on the ca... | 05/06/2008 |
| 7368330 | Semiconductor device having fuse circuit on cell region and method of fabricating the same A semiconductor device, capable of improving integration density and solving problems that may occur in a laser repair process, and a method of fabricating the same are provided. A fuse circuit is formed in a cell region, not in a peripheral region, and thus it is p... | 05/06/2008 |
| 7361993 | Terminal pad structures and methods of fabricating same Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The method... | 04/22/2008 |
| 7358110 | Image sensor having inner lens An image sensor includes an inner lens to enable incident light to reach a condensing lens, so that the incident light may further reach photodiodes. Light loss can be reduced and photosensitivity can be improved. The image sensor includes at least one microlens tha... | 04/15/2008 |
| 7354805 | Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 04/08/2008 |
| 7348516 | Methods of and laser systems for link processing using laser pulses with specially tailored power profiles A laser pulse with a specially tailored temporal power profile, instead of a conventional temporal shape or substantially square shape, severs an IC link. The specially tailored laser pulse preferably has either an overshoot at the beginning of the laser pulse or a ... | 03/25/2008 |
| 7341887 | Integrated circuit die configuration for packaging Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the cor... | 03/11/2008 |
| 7338843 | Method for producing an electronic component, especially a memory chip A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of ... | 03/04/2008 |
| 7334320 | Method of making an electronic fuse with improved ESD tolerance Tolerance to ESD is increased in an electronic fuse by providing at least one non-conductive region adjacent to a conductive region on the surface of an insulator. Such an arrangement reduces the thermal stresses imposed on the insulator in high current applications... | 02/26/2008 |
| 7335537 | Method of manufacturing semiconductor device including bonding pad and fuse elements A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, de... | 02/26/2008 |
| 7323760 | Fuse structure for semiconductor integrated circuit with improved insulation film thickness uniformity and moisture resistance When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even a... | 01/29/2008 |
| 7314815 | Manufacturing method of one-time programmable read only memory An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-typ... | 01/01/2008 |
| 7315193 | Circuitry and method for programming an electrically programmable fuse Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204... | 01/01/2008 |
| 7312101 | Packaged microelectronic devices and methods for packaging microelectronic devices Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second ... | 12/25/2007 |
| 7311852 | Method of plasma etching low-k dielectric materials A semiconductor manufacturing process wherein a low-k dielectric layer is plasma etched with selectivity to an overlying mask layer. The etchant gas can be oxygen-free and include a fluorocarbon reactant, a nitrogen reactant and an optional carrier gas, the fluoroca... | 12/25/2007 |
| 7309628 | Method of forming a semiconductor device A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding... | 12/18/2007 |
| 7309639 | Method of forming a metal trace with reduced RF impedance resulting from the skin effect The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an inc... | 12/18/2007 |
| 7300825 | Customizing back end of the line interconnects Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the two wires, then filling the openings with aluminum. The openings can be... | 11/27/2007 |
| 7294565 | Method of fabricating a wire bond pad with Ni/Au metallization A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN... | 11/13/2007 |
| 7291540 | Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using SOI wafers The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made my producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing... | 11/06/2007 |
| 7282453 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes forming fuse lines over a substrate, forming a first insulation layer over the fuse lines, the first insulation layer including a silicon-rich oxynitride (SRON) layer at the top, forming a second insulation la... | 10/16/2007 |
