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| Number | Title | Issue Date |
| 8148251 | Forming a semiconductor device The present invention includes a method and system for forming a semiconductor device. Varying embodiments generate 2 dimensional alignment features in a device by implementing a 3-dimensional pattern into an underlying device substrate. Accordingly, alignments betw... | 04/03/2012 |
| 7927995 | Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure compri... | 04/19/2011 |
| 7888255 | Method of forming an antifuse and a conductive interconnect, and methods of forming DRAM circuitry A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through insulative material. Then, the first conductor is masked from being exposed through the first via openin... | 02/15/2011 |
| 7786000 | Buried bit line anti-fuse one-time-programmable nonvolatile memory An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.− doped regions. Another N.sup.+ doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.− doped regions on the substrate. An... | 08/31/2010 |
| 7713857 | Methods of forming an antifuse and a conductive interconnect, and methods of forming DRAM circuitry A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through insulative material. Then, the first conductor is masked from being exposed through the first via openin... | 05/11/2010 |
| 7534713 | High density chalcogenide memory cells A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least... | 05/19/2009 |
| 7442626 | Rectangular contact used as a low voltage fuse element A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contac... | 10/28/2008 |
| 7393722 | Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer sel... | 07/01/2008 |
| 7393721 | Semiconductor chip with metallization levels, and a method for formation in interconnect structures A metallization surface (5), which acts as an etching stop layer during the production of openings (4) in a passivation layer (3) applied to its upper face and protects an interconnect structure (6) arranged underneath it, is arranged in ... | 07/01/2008 |
| 7351613 | Method of trimming semiconductor elements with electrical resistance feedback A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through th... | 04/01/2008 |
| 7329565 | Silicide-silicon oxide-semiconductor antifuse device and method of making An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer. ... | 02/12/2008 |
| 7321172 | Selective plating of package terminals In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pa... | 01/22/2008 |
| 7287537 | Megasonic probe energy director A megasonic cleaning apparatus configured to provide effective cleaning of a substrate without causing damage to the substrate is provided. The apparatus includes a megasonic probe, a transducer configured to energize the probe, and a heat transfer element disposed ... | 10/30/2007 |
| 7279772 | Edge intensive antifuse and method for making the same An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 10/09/2007 |
| 7276441 | Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The... | 10/02/2007 |
| 7269898 | Method for making an edge intensive antifuse An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 09/18/2007 |
| 7272067 | Electrically-programmable integrated circuit antifuses Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programmi... | 09/18/2007 |
| 7265001 | Methods of fabricating semiconductor devices Disclosed are methods of fabricating a semiconductor device, by which the pad and fuse layers play their roles smoothly and to enhance a quality of a final semiconductor device. According to one example, a disclosed method includes forming an insulating layer coveri... | 09/04/2007 |
| 7241705 | Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field eff... | 07/10/2007 |
| 7238609 | Method for fabricating semiconductor device A method for fabricating a semiconductor device has the steps of forming a conductive film on a substrate, forming an insulating film such that the conductive film is covered with the insulating film, forming, in the insulating film, a hole having a bottom portion n... | 07/03/2007 |
| 7239299 | Driving circuit of a liquid crystal display device A driving circuit of a liquid crystal display device includes a substrate, at least two driver integrated circuit (IC) chips located on the substrate, and an impedance device electrically connected between the two driver IC chips for reducing a difference between re... | 07/03/2007 |
| 7235858 | Edge intensive antifuse and method for making the same An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 06/26/2007 |
| 7235859 | Arrangement and process for protecting fuses/anti-fuses An arrangement for protecting fuses/anti-fuses on chips which serve to activate redundant circuits or chip functions includes a passivation layer (e.g., hard passivation) arranged on a fully processed chip with the exception of metal contacts of a metallization leve... | 06/26/2007 |
| 7227238 | Integrated fuse with regions of different doping within the fuse neck An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first... | 06/05/2007 |
| 7226816 | Method of forming connection and anti-fuse in layered substrate such as SOI An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as... | 06/05/2007 |
| 7210224 | Method for forming an antifuse An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 05/01/2007 |
| 7206215 | Antifuse having tantalum oxynitride film and method for making same A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electro... | 04/17/2007 |
| 7199473 | Integrated low-k hard mask Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers. ... | 04/03/2007 |
| 7200063 | Circuitry for a programmable element As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage sour... | 04/03/2007 |
| 7196570 | Multiple-time programmable resistance circuit Fuse circuit designs and the use thereof are disclosed. In one example, a fuse circuit providing predictable total resistances for multiple rounds of programming comprises a predetermined number of fuse stages coupled in series. Each stage comprises a first and a se... | 03/27/2007 |
| 7189634 | Edge intensive antifuse An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 03/13/2007 |
| 7183141 | Reversible field-programmable electric interconnects A programmable interconnect structure and method of operating the same provides a programmable interconnection between electrical contacts. The interconnect includes material that has a reversibly programmable resistance. The material includes a molecular matrix wit... | 02/27/2007 |
| 7176064 | Memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide A memory cell is formed of a semiconductor junction diode in series with an antifuse. The cell is programmed by rupture of the antifuse. The semiconductor junction diode comprises silicon, the silicon crystallized in contact with a silicide. The suicide apparently p... | 02/13/2007 |
| 7176065 | Magnetic tunneling junction antifuse device An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least s... | 02/13/2007 |
| 7174351 | Method for deleting stored digital data from write-once memory device A digital storage system is coupled to a write-once memory array. File delete commands are implemented by over-writing a destructive digital pattern to at least a portion of the memory cells associated with the file to be deleted. One disclosed system alters the man... | 02/06/2007 |
| 7173317 | Electrical and thermal contact for use in semiconductor devices An electrical and thermal contact for use in a semiconductor device. The electrical and thermal contact includes an intermediate conductive layer, an insulator component, and a contact layer. The intermediate conductive layer may contact a structure of the semicondu... | 02/06/2007 |
| 7167408 | Circuitry for a programmable element As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage sour... | 01/23/2007 |
| 7160761 | Vertically stacked field programmable nonvolatile memory and method of fabrication A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus ... | 01/09/2007 |
| 7157782 | Electrically-programmable transistor antifuses Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its u... | 01/02/2007 |
| 7157314 | Vertically stacked field programmable nonvolatile memory and method of fabrication A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus ... | 01/02/2007 |
