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| Number | Title | Issue Date |
| 8129201 | Stacking apparatus and method for stacking integrated circuit elements A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit th... | 03/06/2012 |
| 8076164 | On-die bond wires system and method for enhancing routability of a redistribution layer An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads. The relocated bond pads are positioned near an inner edge of the first d... | 12/13/2011 |
| 7989226 | Clocking architecture in stacked and bonded dice A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem w... | 08/02/2011 |
| 7977122 | Fluidic device containing 3D structures A micro fluidic device comprises a laminate structure, comprising a plurality of individual layers. At least one layer comprises a micro fluidic channel structure and at least on one side of said layer a further layer is arranged comprising a three-dimensional (3D) ... | 07/12/2011 |
| 7882482 | Layout schemes and apparatus for high performance DC-DC output stage A layout method that enables a high power switch mode voltage regulator integrated circuit to generate a large output current and achieve substantially low switching loss is disclosed. The layout method includes forming an array of switching elements on a semiconduc... | 02/01/2011 |
| 7723130 | Tooling method for fabricating a semiconductor device and semiconductor devices fabricated thereof A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two... | 05/25/2010 |
| 7615386 | Thick oxide film for wafer backside prior to metalization loop A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick oxide on the wafer backside so that at least pre-selected oxide thickness remains after back end of line pro... | 11/10/2009 |
| 7427517 | Stacking apparatus and method for stacking integrated circuit elements A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit th... | 09/23/2008 |
| 7391117 | Method for fabricating semiconductor components with conductive spring contacts An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer ... | 06/24/2008 |
| 7382363 | Microencapsulated electrophoretic display with integrated driver A mounted display assembly comprises a flexible substrate that supports both display elements and control circuits. The display assembly generally comprises: an electrical connection formed on the flexible substrate, the electrical connection having first and second... | 06/03/2008 |
| 7378287 | Wafer matching methods for use in assembling micromirror array devices The invention provides a method for matching micromirror wafers and electrode wafers so as to form micromirror array devices while the production yield is maximized. Each micromirror wafer and/or electrode wafer may have one or more non-passing dies and a plurality ... | 05/27/2008 |
| 7368374 | Super high density module with integrated wafer level packages A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packa... | 05/06/2008 |
| 7356656 | Skew free control of a multi-block SRAM A multi-block SRAM memory system is described where a single global clock pulse is distributed to each memory block from the central control. At each SRAM memory block a local signal generator uses the globally distributed clock pulse to generate the required memory... | 04/08/2008 |
| 7348263 | Manufacturing method for electronic component, electronic component, and electronic equipment A manufacturing method for electronic device, includes: preparing a first substrate having a plurality of first regions; preparing a second substrate having a plurality of second regions; facing the first region and the second region each other, and connecting the f... | 03/25/2008 |
| 7338843 | Method for producing an electronic component, especially a memory chip A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of ... | 03/04/2008 |
| 7335972 | Heterogeneously integrated microsystem-on-a-chip A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect struct... | 02/26/2008 |
| 7329549 | Monitoring method of processing state and processing unit The present invention is a monitoring method of monitoring a change of a processing state of an object to be processed when a predetermined process is conducted to the object to be processed by using a processing unit. The method includes: a step of respectively set... | 02/12/2008 |
| 7323751 | Thin film resistor integration in a dual damascene structure A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over t... | 01/29/2008 |
| 7316786 | Method of polishing film to be polished A method is provided that includes a main laminate making step of forming a plurality of main magnetic poles onto a substrate, covering each magnetic pole with a first protective film, and forming onto the first protective film a stopper film provided with openings ... | 01/08/2008 |
| 7316934 | Personalized hardware A system for personalizing one or more electrical circuits having plurality of layers with electrical characteristics. The layers being produced by an electrical characteristic determination process (ECDP). The system for personalizing includes a wafer stage for rec... | 01/08/2008 |
| 7314821 | Method for fabricating a semiconductor interconnect having conductive spring contacts An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer ... | 01/01/2008 |
| 7302982 | Label applicator and system A label applicator including a support surface having a central area and curving downwardly from the central area. A post assembly extends up from the central area such that a label having a label through-hole can be positioned in a support position generally on the... | 12/04/2007 |
| 7282374 | Method and apparatus for comparing device and non-device structures The present invention provides a method and apparatus for comparing device and non-device structures. The method includes determining at least one characteristic parameter associated with at least one non-device structure on at least one workpiece and determining at... | 10/16/2007 |
| 7279419 | Formation of self-aligned contact plugs Methods of forming a contact structure for semiconductor assemblies are described. One method provides process steps to create an inner dielectric isolation layer after the contact region is protected, which is followed by the formation of the self-aligned contact s... | 10/09/2007 |
| 7271047 | Test structure and method for measuring the resistance of line-end vias A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is... | 09/18/2007 |
| 7265001 | Methods of fabricating semiconductor devices Disclosed are methods of fabricating a semiconductor device, by which the pad and fuse layers play their roles smoothly and to enhance a quality of a final semiconductor device. According to one example, a disclosed method includes forming an insulating layer coveri... | 09/04/2007 |
| 7263682 | System and method for calculating trace lengths of a PCB layout A system for calculating trace lengths of a PCB layout includes a computer (10) and a database (11). The computer includes: an object setting module (100) for setting objects to define section rules; a section rule defining module (101) f... | 08/28/2007 |
| 7259043 | Circular test pads on scribe street area A semiconductor wafer design and process having test pads (36) reducing cracks generated during the wafer saw process from extending into and damaging adjacent die. The present invention provides a plurality of circular test pads (36) in a wafer scribe... | 08/21/2007 |
| 7258838 | Solid state molecular probe device A solid state nanopore device including two or more materials and a method for fabricating the same. The device includes a solid state insulating membrane having an exposed surface, a conductive material disposed on at least a portion of the exposed surface of the s... | 08/21/2007 |
| 7256668 | Phase change control devices and circuits for guiding electromagnetic waves employing phase change control devices A circuit for guiding electromagnetic waves includes a substrate for supporting components of the circuit. The circuit includes a control device which includes a first conductive element on the substrate for connection to a first component of the circuit and a secon... | 08/14/2007 |
| 7247562 | Semiconductor element, semiconductor device and methods for manufacturing thereof The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield ... | 07/24/2007 |
| 7242012 | Lithography device for semiconductor circuit pattern generator General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 07/10/2007 |
| 7223696 | Methods for maskless lithography General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 05/29/2007 |
| 7220636 | Process for controlling performance characteristics of a negative differential resistance (NDR) device A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operation... | 05/22/2007 |
| 7214594 | Method of making semiconductor device using a novel interconnect cladding layer A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive in... | 05/08/2007 |
| 7214569 | Apparatus incorporating small-feature-size and large-feature-size components and method for making same An apparatus incorporating small-feature size and large-feature-size components. The apparatus comprise a strap including a substrate with an integrated circuit contained therein. The integrated circuit coupling to a first conductor disposed on the substrate. The fi... | 05/08/2007 |
| 7193239 | Three dimensional structure integrated circuit A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, red... | 03/20/2007 |
| 7179661 | Chemical mechanical polishing test structures and methods for inspecting the same Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment... | 02/20/2007 |
| 7176040 | Inkjet-fabricated integrated circuits A method for forming an integrated circuit including at least two interconnected electronic switching devices, the method comprising forming at least part of the electronic switching devices by ink-jet printing. ... | 02/13/2007 |
| 7176545 | Apparatus and methods for maskless pattern generation General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 02/13/2007 |
