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Pet Toilet-Like Water Disk and Food Storage
One pet-friendly inventor patented "a device for watering pets, e.g., a dog or cat." The device, he helpfully noted, "has the general shape of a toilet."
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| Number | Title | Issue Date |
| 8178434 | On-chip embedded thermal antenna for chip cooling An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connect... | 05/15/2012 |
| 8043953 | Semiconductor device including an LSI chip and a method for manufacturing the same A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an in... | 10/25/2011 |
| 8017512 | Efficient power management method in integrated circuit through a nanotube structure Efficient power management method in integrated circuit through a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer of an integrated circuit. The transistor layer may be above a semic... | 09/13/2011 |
| 7994042 | Techniques for impeding reverse engineering Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one... | 08/09/2011 |
| 7939443 | Methods for multi-wire routing and apparatus implementing same A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, ... | 05/10/2011 |
| 7851344 | Method of producing a substrate having areas of different hydrophilicity and/or oleophilicity on the same surface The present invention relates to flexible substrates having on their surface a wetting contrast. The wetting contrast comprises adjacent areas of different hydrophilicity and/or oleophilicity. The present invention further relates to methods of production of such su... | 12/14/2010 |
| 7838409 | Structures and methods for an application of a flexible bridge One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface... | 11/23/2010 |
| 7825019 | Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal l... | 11/02/2010 |
| 7767573 | Layout for high density conductive interconnects In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each othe... | 08/03/2010 |
| 7763534 | Methods, structures and designs for self-aligning local interconnects used in integrated circuits Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to b... | 07/27/2010 |
| 7638417 | Electronic circuit with repetitive patterns formed by shadow mask vapor deposition and a method of manufacturing an electronic circuit element An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of depositi... | 12/29/2009 |
| 7521349 | Fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus The present invention provides a fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus for designing a layout of a functional circuit block or a semiconductor integrated circuit device using the fundamental cells, with a highe... | 04/21/2009 |
| 7494910 | Methods of forming semiconductor package The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention ... | 02/24/2009 |
| 7452796 | Semi-conductor device with inductive component and method of making An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as cop... | 11/18/2008 |
| 7413981 | Pitch doubled circuit layout In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry includes providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other... | 08/19/2008 |
| 7396750 | Method and structure for contacting two adjacent GMR memory bit A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via. ... | 07/08/2008 |
| 7393794 | Pattern formation method After forming a resist film including a hygroscopic compound, pattern exposure is performed by selectively irradiating the resist film with exposing light while supplying water onto the resist film. After the pattern exposure, the resist film is developed so as to f... | 07/01/2008 |
| 7387912 | Packaging of electronic chips with air-bridge structures A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structur... | 06/17/2008 |
| 7378339 | Barrier for use in 3-D integration of circuits A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circ... | 05/27/2008 |
| 7377032 | Process for producing a printed wiring board for mounting electronic components A printed wiring board for mounting electronic components includes an insulating layer and a wiring pattern formed on one surface of the insulating layer, wherein one end portion of a filled via 4 is connected with the wiring pattern and the other end portion... | 05/27/2008 |
| 7365006 | Semiconductor package and substrate having multi-level vias fabrication method A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of ... | 04/29/2008 |
| 7338824 | Method for manufacturing FFS mode LCD In the present invention, a method for manufacturing a liquid crystal display is provided. The method includes steps of providing a substrate, forming a first metal layer on the substrate, etching the first metal layer to form a plurality of gate lines on the substr... | 03/04/2008 |
| 7335583 | Isolating semiconductor device structures An array of continuous diffusion regions and continuous gate electrode structures is formed over a semiconductor substrate. Interconnecting diffusion region portions and interconnecting gate electrode portions are removed to electrically isolate transistor circuitry... | 02/26/2008 |
| 7335517 | Multichip semiconductor device, chip therefor and method of formation thereof A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the c... | 02/26/2008 |
| 7332378 | Integrated circuit memory system with dummy active region An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming s... | 02/19/2008 |
| 7316972 | Contact hole formation method A contact hole formation method includes a process of depositing a BPSG film 4 on a semiconductor substrate 1 on which transistors are formed, a process of planarizing the BPSG film 4, a process of depositing a dielectric film 5 on the BP... | 01/08/2008 |
| 7306977 | Method and apparatus for facilitating signal routing within a programmable logic device Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs ... | 12/11/2007 |
| 7302651 | Technology migration for integrated circuits with radical design restrictions A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach th... | 11/27/2007 |
| 7302665 | Method and apparatus for designing a layout, and computer product An apparatus for designing a layout includes an arranging unit that arranges, on a large-scale-integrated chip, a cell in which a signal line segment that is not connected to a terminal is formed; a wiring unit that wires a signal line to an arbitrary wiring layer o... | 11/27/2007 |
| 7294534 | Interconnect layout method In an interconnect layout 100, the first gate pattern, the second gate pattern, the first dummy pattern, and the second dummy pattern are arranged so that, if a wavelength of a light used to expose the first gate pattern and the second gate pattern is λ, natural nu... | 11/13/2007 |
| 7283381 | System and methods for addressing a matrix incorporating virtual columns and addressing layers A system and methods for addressing unique locations in a matrix. According to some embodiments, the system includes a plurality of uniquely addressable locations. A plurality of virtual columns that include a plurality of serially connected switch elements provide ... | 10/16/2007 |
| 7274268 | Balun with structural enhancements A balun including a pair of metal coil structures and an intervening dielectric layer having a thickness that is selected in response an operating frequency of the balun. The thickness of the dielectric layer may be used to tune the balun and enhance its self-induct... | 09/25/2007 |
| 7271086 | Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes constructing a dielectric structure on a microfeature workpiece having a ... | 09/18/2007 |
| 7249336 | Automatic wiring method for semiconductor integrated circuit, program for the same, and semiconductor integrated circuit A controller arranges macrocells having power terminals and ground terminals in desired positions on a semiconductor chip. The power terminals and ground terminals are arranged in a fourth line layer such that the centers of square power terminals and ground termina... | 07/24/2007 |
| 7243441 | Method and apparatus for measuring depth of holes formed on a specimen A method an apparatus for measuring the depths of many fine holes formed in the surface of a sample by etching. Positional information on a plurality of hole patterns is acquired by scanning, with a stylus, the surface of the sample in which the hole patterns are fo... | 07/17/2007 |
| 7234232 | Methods for designing and tuning one or more packaged integrated circuits A method for producing and tuning a packaged integrated circuit a) incorporates into a packaged integrated circuit design, at least one tunable circuit feature; b) fabricates a packaged integrated circuit in accordance with said packaged integrated circuit design; c... | 06/26/2007 |
| 7226825 | Method of fabricating micro-chips A method of fabricating micro-chips, including: (a) providing a substrate; (b) forming a first single-crystal layer on a top surface of the substrate; (c) forming a second single-crystal layer on a top surface of the first single-crystal layer; (d) forming integrate... | 06/05/2007 |
| 7226839 | Method and system for improving the topography of a memory array A method and system for improving the topography of a memory array is disclosed. In one embodiment, a dummy bitline is formed over a field oxide region at an interface between a memory array and interface circuitry. In addition, a poly-2 layer is applied above the d... | 06/05/2007 |
| 7214551 | Multiple gate electrode linewidth measurement and photoexposure compensation method A method for fabricating a semiconductor product first provides an embedded semiconductor product comprising: (1) a logic region having formed therein a logic field effect transistor device; (2) a memory region having formed therein a memory field effect transistor ... | 05/08/2007 |
| 7208410 | Methods relating to forming interconnects Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component substrate, such as a semiconductor die or other substrate, has dielectric m... | 04/24/2007 |
