Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 8158505 | Method for manufacturing a semiconductor device, semiconductor chip and semiconductor wafer A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions f... | 04/17/2012 |
| 8071468 | Semiconductor device and method of manufacturing semiconductor device There is provided a method of manufacturing a semiconductor device, the method including performing at least one of: processing, when forming the first redistribution layer, of forming the first electrically conductive material layer by growing the first electricall... | 12/06/2011 |
| 8053349 | BGA package with traces for plating pads under the chip A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the ... | 11/08/2011 |
| 7994041 | Method of manufacturing stacked semiconductor package using improved technique of forming through via A method of manufacturing a stacked semiconductor package using an improved technique of forming a through via in order to enable 3-dimensional vertical interconnection of stacked packages is provided. The method includes forming a seed layer required for forming a ... | 08/09/2011 |
| 7977229 | Method for fabricating resin-molded semiconductor device having posts with bumps A semiconductor apparatus includes a semiconductor device to be mounted on a circuit board; a plurality of conductive posts electrically connected to the semiconductor device; and a plurality of conductive bumps each provided on an outer end of each of the conductiv... | 07/12/2011 |
| 7960269 | Method for forming a double embossing structure A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; deposi... | 06/14/2011 |
| 7935621 | Anti-fuse device structure and electroplating circuit structure and method Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical po... | 05/03/2011 |
| 7879711 | Stacked structures and methods of fabricating stacked structures A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure forme... | 02/01/2011 |
| 7875544 | Method of producing a semiconductor interconnect architecture including generation of metal holes by via mutation A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs... | 01/25/2011 |
| 7867886 | Method of enclosing a micro-electromechanical element A method, in a complementary metal oxide semiconductor fabrication process, of creating a layered housing containing a micro-electromechanical system device, the method comprising the steps of providing a cavity in at least one layer of the housing, the cavity being... | 01/11/2011 |
| 7858510 | Interfacial layers for electromigration resistance improvement in damascene interconnects Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a first layer of aluminum-containing mater... | 12/28/2010 |
| 7838408 | Semiconductor device, wafer and method of designing and manufacturing the same A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interc... | 11/23/2010 |
| 7833894 | Devices and systems having at least one dam structure A method for forming through-wafer interconnects (TWI) in a substrate. Blind holes are formed from a surface, sidewalls thereof are passivated and coated with a conductive material. A vent hole is then formed from the opposite surface to intersect the blind hole. Th... | 11/16/2010 |
| 7833895 | TSVS having chemically exposed TSV tips for integrated circuit devices A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedde... | 11/16/2010 |
| 7799671 | Interfacial layers for electromigration resistance improvement in damascene interconnects Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a source layer of dopant-generating materi... | 09/21/2010 |
| 7727872 | Methods for fabricating semiconductor components with conductive interconnects A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the... | 06/01/2010 |
| 7704868 | Fabrication of a micro-electromechanical system (MEMS) device from a complementary metal oxide semiconductor (CMOS) Methods of fabricating micro-electromechanical system devices from complementary metal oxide semiconductors (CMOS) are provided. ... | 04/27/2010 |
| 7648899 | Interfacial layers for electromigration resistance improvement in damascene interconnects Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a source layer of dopant-generating materi... | 01/19/2010 |
| 7645693 | Semiconductor device and programming method therefor A semiconductor device includes bit lines (14) provided in a semiconductor substrate (10), word lines (16) provided above the bit lines and running in a width direction of the bit lines (14), metal lines (22) provided above the wor... | 01/12/2010 |
| 7632747 | Conductive structures for microfeature devices and methods for fabricating microfeature devices Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plura... | 12/15/2009 |
| 7611981 | Optimized circuit design layout for high performance ball grid array packages A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough f... | 11/03/2009 |
| 7560370 | Method for manufacturing semiconductor device A method for forming a semiconductor device includes forming a bit line contact region with a line pattern and then performing a process to form a bit line so that a multi-layered bit line contact is expended, thereby preventing a short between bit line contact plug... | 07/14/2009 |
| 7531439 | Method for forming an integrated semiconductor circuit arrangement Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material ... | 05/12/2009 |
| 7524753 | Semiconductor device having through electrode and method of manufacturing the same A method of manufacturing a semiconductor device having a through electrode, includes forming through holes 36 in a substrate 31, forming a first metal layer 39 from one surface side of the substrate and pasting a protection film 40 on on... | 04/28/2009 |
| 7494909 | Method of manufacturing a chip Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a ... | 02/24/2009 |
| 7491636 | Methods for forming flexible column die interconnects and resulting structures A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad an... | 02/17/2009 |
| 7439168 | Apparatus and method of forming silicide in a localized manner Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localize... | 10/21/2008 |
| 7439623 | Semiconductor device having via connecting between interconnects A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed... | 10/21/2008 |
| 7435674 | Dielectric interconnect structures and methods for forming the same Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is... | 10/14/2008 |
| 7410892 | Methods of fabricating integrated circuit devices having self-aligned contact structures An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first in... | 08/12/2008 |
| 7396751 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming a second storage node contact hole with a mask for storage node and securing an overlay margin between a storage node contact hole and a storage node with a hard mask layer that serves as a hard mask... | 07/08/2008 |
| 7393770 | Backside method for fabricating semiconductor components with conductive interconnects A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of ... | 07/01/2008 |
| 7393794 | Pattern formation method After forming a resist film including a hygroscopic compound, pattern exposure is performed by selectively irradiating the resist film with exposing light while supplying water onto the resist film. After the pattern exposure, the resist film is developed so as to f... | 07/01/2008 |
| 7391117 | Method for fabricating semiconductor components with conductive spring contacts An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer ... | 06/24/2008 |
| 7372155 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length-by making efficient use of polyimide or polymer as an ... | 05/13/2008 |
| 7368767 | Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a ... | 05/06/2008 |
| 7354842 | Methods of forming conductive materials The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to rele... | 04/08/2008 |
| 7348270 | Techniques for forming interconnects A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect m... | 03/25/2008 |
| 7348249 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device reduces or prevents copper contamination. The method includes forming a gate electrode on a substrate; forming a first oxide layer on a front surface of the substrate including the gate electrode; depositing a nitrid... | 03/25/2008 |
| 7339274 | Metallization performance in electronic devices Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planaritie... | 03/04/2008 |
