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| Number | Title | Issue Date |
| 8173533 | Semiconductor memory device and method of forming the same Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through t... | 05/08/2012 |
| 8163641 | System for modifying small structures A charge transfer mechanism is used to locally deposit or remove material for a small structure. A local electrochemical cell is created without having to immerse the entire work piece in a bath. The charge transfer mechanism can be used together with a charged part... | 04/24/2012 |
| 8093146 | Method of fabricating gate electrode using a hard mask with spacers A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a hard mask layer over the gate material layers; patter... | 01/10/2012 |
| 7923365 | Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when ... | 04/12/2011 |
| 7855135 | Method to reduce parastic capacitance in a metal high dielectric constant (MHK) transistor A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer o... | 12/21/2010 |
| 7767569 | Method of manufacturing semiconductor device Method of forming a high-reliability contact plug which prevents a short circuit between the plug and a bit line by applying a material having an etching rate ratio of 100 or more with respect to a silicon nitride film which forms a self-aligned contact plug. After ... | 08/03/2010 |
| 7582550 | Semiconductor memory device and manufacturing method thereof A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side o... | 09/01/2009 |
| 7504330 | Method of forming an insulative film A method of forming an insulative film includes a step of vacuum laminating an insulative organic material on a substrate that has a peripheral ring electrode formed in a peripheral region of the substrate and a device element(s) formed inside the peripheral region,... | 03/17/2009 |
| 7498248 | Methods of compensating for an alignment error during fabrication of structures on semiconductor substrates In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of f... | 03/03/2009 |
| 7435673 | Methods of forming integrated circuit devices having metal interconnect structures therein Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insul... | 10/14/2008 |
| 7429527 | Method of manufacturing self-aligned contact openings A method of manufacturing self-aligned contact openings is provided. A substrate having a number of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are se... | 09/30/2008 |
| 7419870 | Method of manufacturing a flash memory device Provided is a method of manufacturing a flash memory device. In the method, after forming a cell string and source/drain selection transistors, it forms a first oxide film in which a sidewall oxide film and a buffering oxide film are stacked, a nitride film, and a s... | 09/02/2008 |
| 7371669 | Method of forming a gate of a semiconductor device In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on ... | 05/13/2008 |
| 7368373 | Method for manufacturing semiconductor devices and plug A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a s... | 05/06/2008 |
| 7368347 | Dual bit flash memory devices and methods for fabricating the same Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided ove... | 05/06/2008 |
| 7358552 | Complementary metal-oxide-semiconductor image sensor and method for fabricating the same A complementary metal-oxide-semiconductor (CMOS) image sensor and a method for fabricating the same are provided. The CMOS image sensor includes: a pixel region provided with a plurality of unit pixels, each including a buried photodiode and a floating diffusion reg... | 04/15/2008 |
| 7348266 | Method and apparatus for a metallic dry-filling process An iPVD system is programmed to deposit uniform material, such as a metallic material, into high aspect ratio nano-sized features on semiconductor substrates using a process that enhances the feature filling compared to the field deposition, while maximizing the siz... | 03/25/2008 |
| 7332433 | Methods of modulating the work functions of film layers Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where t... | 02/19/2008 |
| 7329595 | Deposition of carbon-containing layers using vitreous carbon source An effusion source comprises a vitreous C filament and a heater to increase the temperature of the filament to produce a C vapor. Also described is a deposition method comprising (a) depositing a layer of material on a substrate, and (b) during step (a), heating a b... | 02/12/2008 |
| 7320913 | Methods of forming split-gate non-volatile memory devices Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming... | 01/22/2008 |
| 7320914 | System and method for gate formation in a semiconductor device A method for forming a memory device is provided. A first layer is formed over a substrate. A second layer is formed over the first layer. A mask is formed over the second layer. Spacers are formed adjacent opposite sides of the mask. The second layer is etched to f... | 01/22/2008 |
| 7312129 | Method for producing two gates controlling the same channel A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) t... | 12/25/2007 |
| 7312499 | Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function o... | 12/25/2007 |
| 7306992 | Flash memory device and method of fabricating the same A flash memory device includes control gates that are formed to completely surround the top and sides of floating gates. The control gates are located between the floating gates that are adjacent in the word line direction as well as the floating gates that are adja... | 12/11/2007 |
| 7300843 | Method of fabricating flash memory device A method of fabricating a flash memory device is disclosed wherein, electrode spacers are formed on sides of self-aligned floating gates having a negative slope. Thus, upon etching of a stack gate after an interlayer dielectric film and a control gate are formed, a ... | 11/27/2007 |
| 7297595 | Non-volatile memory device and fabricating method thereof The present invention provides a non-volatile memory device and fabricating method thereof, in which a height of a floating gate conductor layer pattern is sustained without lowering a degree of integration and by which a coupling ratio is raised. The present invent... | 11/20/2007 |
| 7276433 | Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one im... | 10/02/2007 |
| 7273783 | Methods for reducing void formation in semiconductor devices A method of forming a semiconductor device includes forming an insulating layer on a semiconductor substrate. The insulating layer has a trench therein with opposing sidewalls and a bottom surface. A first conductive layer is formed on the sidewalls and on the botto... | 09/25/2007 |
| 7271052 | Long retention time single transistor vertical memory gain cell A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lowe... | 09/18/2007 |
| 7268042 | Nonvolatile semiconductor memory and making method thereof A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then repla... | 09/11/2007 |
| 7262089 | Methods of forming semiconductor structures The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for ex... | 08/28/2007 |
| 7259098 | Methods for fabricating semiconductor devices Semiconductor devices and methods for fabricating a semiconductor devices are disclosed. A disclosed method comprises: forming a first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate... | 08/21/2007 |
| 7238601 | Semiconductor device having conductive spacers in sidewall regions and method for forming A conductive spacer (36, 122) in a sidewall region (30, 16) of a device (10, 100) is formed. The conductive spacer is formed adjacent sidewalls of the current electrode regions (18, 12). In one embodiment, a thin silicide layer (34... | 07/03/2007 |
| 7226838 | Methods for fabricating a semiconductor device Methods of fabricating a semiconductor device is disclosed. An illustrated method comprises: providing a substrate including an active region and a non-active region; forming a first gate electrode including a dielectric layer pattern, a first conducting layer patte... | 06/05/2007 |
| 7217624 | Non-volatile memory device with conductive sidewall spacer and method for fabricating the same The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on ... | 05/15/2007 |
| 7214585 | Methods of fabricating integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges A widened contact area (170X) of a conductive feature (170) is formed by means of self-alignment between an edge (170E2) of the conductive feature and an edge (140E) of another feature (140). The other feature (“first feat... | 05/08/2007 |
| 7208805 | Structures comprising a layer free of nitrogen between silicon nitride and photoresist The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first ma... | 04/24/2007 |
| 7205234 | Method of forming metal silicide A method of optimizing the formation of nickel silicide on regions of a MOSFET structure, has been developed. The method features formation of nickel silicide using an anneal procedure performed at a temperature below which nickel silicide instability and agglomerat... | 04/17/2007 |
| 7186633 | Method and structure for tungsten gate metal surface treatment while preventing oxidation As disclosed herein, an FEOL line conductor stack is formed including a base conductor layer, an overlying layer of tungsten, and an optional gate capping layer. The stack, including layers from the optional capping layer down to the base conductor layer are directi... | 03/06/2007 |
| 7176084 | Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielect... | 02/13/2007 |
