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| Number | Title | Issue Date |
| 8114764 | Semiconductor device and fabrication method thereof A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate unde... | 02/14/2012 |
| 8084346 | Replacement metal gate method A method includes forming a dummy gate in a dielectric layer on a substrate, the dummy gate including a sacrificial oxide layer and a dummy gate body over the sacrificial oxide layer; removing the dummy gate body resulting in a gate opening with the sacrificial oxid... | 12/27/2011 |
| 8053348 | Method of forming a semiconductor device using a sacrificial uniform vertical thickness spacer structure Disclosed is a method of forming planar and non-planar semiconductor devices using a sacrificial gate sidewall spacer with a uniform vertical thickness. The method forms such spacers by selectively growing an epitaxial film on the vertical sidewalls of a gate struct... | 11/08/2011 |
| 8048792 | Superior fill conditions in a replacement gate approach by corner rounding prior to completely removing a placeholder material In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder materi... | 11/01/2011 |
| 8039381 | Photoresist etch back method for gate last process A method is provided for fabricating a semiconductor device. The method includes providing a substrate including a dummy gate structure formed thereon, removing the dummy gate structure to form a trench, forming a first metal layer over the substrate to fill a porti... | 10/18/2011 |
| 7994040 | Semiconductor device and fabrication thereof A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode la... | 08/09/2011 |
| 7989333 | Methods of forming integrated circuit devices having anisotropically-oxidized nitride layers Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first po... | 08/02/2011 |
| 7906419 | Laser annealing method for manufacturing semiconductor device A laser annealing method for manufacturing a semiconductor device is presented. The method includes at least two forming steps and one annealing step. The first forming steps includes forming gates on a semiconductor substrate. The second forming step includes formi... | 03/15/2011 |
| 7897501 | Method of fabricating a field-effect transistor having robust sidewall spacers A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a secon... | 03/01/2011 |
| 7833892 | Method of forming a field effect transistor The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one im... | 11/16/2010 |
| 7820539 | Method for separately optimizing spacer width for two transistor groups using a recess spacer etch (RSE) integration A method for making a semiconductor device is provided. In accordance with the method, a semiconductor structure is provided which comprises (a) a substrate (203), (b) first (219) and second (220) gate electrodes disposed over the substrate, and... | 10/26/2010 |
| 7776732 | Metal high-K transistor having silicon sidewall for reduced parasitic capacitance, and process to fabricate same A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer o... | 08/17/2010 |
| 7749880 | Method of manufacturing semiconductor integrated circuit device In a method of manufacturing a semiconductor integrated circuit device, a gate electrode is formed over a semiconductor substrate. An insulating film is then formed on the gate electrode and on regions corresponding to a source and a drain of the semiconductor integ... | 07/06/2010 |
| 7745320 | Method for reducing silicide defects in integrated circuits A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the... | 06/29/2010 |
| 7737019 | Method for containing a silicided gate within a sidewall spacer in integrated circuit technology A method of forming an integrated circuit includes providing a semiconductor substrate and forming a gate over the semiconductor substrate. A gate sidewall spacer is formed around the gate and a resist is deposited on the gate sidewall spacer with the gate sidewall ... | 06/15/2010 |
| 7700473 | Gated semiconductor device and method of fabricating same A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting ma... | 04/20/2010 |
| 7682956 | Three-dimensional metal microfabrication process and devices produced thereby The present invention relates, in general, to a method for three-dimensional (3D) microfabrication of complex, high aspect ratio structures with arbitrary surface height profiles in metallic materials, and to devices fabricated in accordance with this process. The m... | 03/23/2010 |
| 7678679 | Vertical device with sidewall spacer, methods of forming sidewall spacers and field effect transistors, and patterning method A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like s... | 03/16/2010 |
| 7589006 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming a plurality of gate lines on a substrate, forming a first cell spacer on the gate lines, forming a second cell spacer on the first cell spacer, forming a buffer layer on the second cell spacer, and e... | 09/15/2009 |
| 7538018 | Gate structure and method for fabricating the same, and method for fabricating memory and CMOS transistor layout A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive... | 05/26/2009 |
| 7534711 | System and method for direct etching System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a substrate having a contact region, which is provided between a first ... | 05/19/2009 |
| 7470606 | Masking methods The invention includes masking methods. In one implementation, a masking material which includes boron doped amorphous carbon is formed over a feature formed on a semiconductor substrate. The masking material includes at least about 0.5 atomic percent boron. The mas... | 12/30/2008 |
| 7462554 | Method for forming semiconductor device with modified channel compressive stress A method for forming a semiconductor device provides for forming a gate region on top of a substrate. Gate sidewall liners are formed on opposed sides of the gate region, the sidewall liners having a vertical part contacting sidewalls of the gate region and a horizo... | 12/09/2008 |
| 7459384 | Preventing cavitation in high aspect ratio dielectric regions of semiconductor device Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures... | 12/02/2008 |
| 7439138 | Method of forming integrated circuitry The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one im... | 10/21/2008 |
| 7425498 | Semiconductor device with dummy electrode A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact port... | 09/16/2008 |
| 7422971 | Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of formin... | 09/09/2008 |
| 7419876 | Method for manufacturing non-volatile memory devices integrated in a semiconductor substrate A method manufactures non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: forming a plurality of electrodes of the matrix memory cells, e... | 09/02/2008 |
| 7420202 | Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and... | 09/02/2008 |
| 7413970 | Process of forming an electronic device including a semiconductor fin An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-ap... | 08/19/2008 |
| 7413957 | Methods for forming a transistor Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate ... | 08/19/2008 |
| 7410876 | Methodology to reduce SOI floating-body effect A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode (207) disposed on a substrate (203); (b) creating first (213) and second (214) pre-amorphization implant regions in the substrate... | 08/12/2008 |
| 7402484 | Methods for forming a field effect transistor Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate electrode and the substrate. ... | 07/22/2008 |
| 7399689 | Methods for manufacturing semiconductor memory devices using sidewall spacers Storage nodes for semiconductor memory devices may be fabricated by repeatedly forming conductive and insulating spacers on mold oxide layer pattern sidewalls, to thereby obtain fine line patterns which can increase the surface area of the storage node electrodes. S... | 07/15/2008 |
| 7399690 | Methods of fabricating semiconductor devices and structures thereof Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is d... | 07/15/2008 |
| 7396716 | Method to obtain fully silicided poly gate The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures ... | 07/08/2008 |
| 7381623 | Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second ga... | 06/03/2008 |
| 7378308 | CMOS devices with improved gap-filling A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the ... | 05/27/2008 |
| 7378323 | Silicide process utilizing pre-amorphization implant and second spacer A gate electrode is formed on a substrate with a gate insulating layer therebetween. A liner is then deposited on sidewalls of the gate electrode. Source/drain extensions are implanted into the substrate. A first spacer is then formed on the liner. Deep source/drain... | 05/27/2008 |
| 7374635 | Forming method and forming system for insulation film A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) ar... | 05/20/2008 |
