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| Number | Title | Issue Date |
| 8097531 | Methods of manufacturing charge trap type memory devices Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be ... | 01/17/2012 |
| 8043952 | Method of forming aluminum oxide layer and method of manufacturing charge trap memory device using the same Provided is a method of forming an aluminum oxide layer and a method of manufacturing a charge trap memory device using the same. The method of forming an aluminum oxide layer may include forming an amorphous aluminum oxide layer on an underlying layer, forming a cr... | 10/25/2011 |
| 7981786 | Method of fabricating non-volatile memory device having charge trapping layer A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate el... | 07/19/2011 |
| 7927994 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between ... | 04/19/2011 |
| 7923364 | Tunnel dielectric comprising nitrogen for use with a semiconductor device and a process for forming the device A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor typ... | 04/12/2011 |
| 7915156 | Semiconductor memory device and method for manufacturing the same A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling ... | 03/29/2011 |
| 7825018 | Plasma oxidation method and method for manufacturing semiconductor device A plasma oxidation processing method is performed, on a structural object including a silicon layer and a refractory metal-containing layer, to form a silicon oxide film. A first plasma oxidation process is performed by use of a process gas including at least hydrog... | 11/02/2010 |
| 7741203 | Method of forming gate pattern of flash memory device including over etch with argon A method of forming a gate pattern of a flash memory device may include forming a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, a metal electrode layer, and a hard mask film over a semicon... | 06/22/2010 |
| 7727871 | Manufacturing method of semiconductor device using etching solution This disclosure concerns a manufacturing method of a semiconductor device comprising an etching process using an etching solution having ozone dissolved by 10 ppm or more into a liquid containing H2SO4 by 86 wt % to 97.9 wt %, HF by 0.1 wt % to... | 06/01/2010 |
| 7704867 | Method of manufacturing semiconductor devices In semiconductor devices and methods of manufacturing semiconductor devices, a zirconium source having zirconium, carbon and nitrogen is provided onto a substrate to form an adsorption layer of the zirconium source on the substrate. A first purging process is perfor... | 04/27/2010 |
| 7629245 | Method of forming non-volatile memory device A method of fabricating a non-volatile memory device, wherein a gate insulating layer, a first conductive layer, a tunneling layer, a trap nitride layer, a blocking oxide layer, and a capping layer are sequentially formed over a semiconductor substrate of a peripher... | 12/08/2009 |
| 7534710 | Coupled quantum well devices (CQWD) containing two or more direct selective contacts and methods of making same The present invention relates to a device structure that contains two or more conducting layers, two peripheral insulating layers, one or more intermediate insulating layers, and two or more conductive contacts. The two or more conducting layers are sandwiched betwe... | 05/19/2009 |
| 7439131 | Flash memory device having resistivity measurement pattern and method of forming the same A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the r... | 10/21/2008 |
| 7425489 | Self-aligned shallow trench isolation A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer... | 09/16/2008 |
| 7407857 | Method of making a scalable flash EEPROM memory cell with notched floating gate and graded source region An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulat... | 08/05/2008 |
| 7335593 | Method of fabricating semiconductor device A gate metal is formed in a film, the foregoing gate metal is partially etched per each TFT having a different property, and a gate electrode is fabricated. Specifically, a resist mask is fabricated by exposing a resist to light per each TFT having a different prope... | 02/26/2008 |
| 7304344 | Integrated circuit having independently formed array and peripheral isolation dielectrics The invention comprises a method of forming an integrated circuit, the method comprising: (1) forming a first dielectric layer disposed outwardly from a semiconductor substrate; (2) forming a first intermediate structure outwardly from the a dielectric layer, the fi... | 12/04/2007 |
| 7285464 | Nonvolatile memory cell comprising a reduced height vertical diode A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped ... | 10/23/2007 |
| 7279385 | Flash memory device and manufacturing method thereof A method of manufacturing a flash memory device is provided. Multiple stack structures each comprising a tunneling oxide layer and a first conductive layer are formed over a substrate. Thereafter, multiple embedded doping regions is formed in the substrate between t... | 10/09/2007 |
| 7273783 | Methods for reducing void formation in semiconductor devices A method of forming a semiconductor device includes forming an insulating layer on a semiconductor substrate. The insulating layer has a trench therein with opposing sidewalls and a bottom surface. A first conductive layer is formed on the sidewalls and on the botto... | 09/25/2007 |
| 7269067 | Programming a memory device A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applyi... | 09/11/2007 |
| 7259422 | Nonvolatile semiconductor memory device and its fabrication method A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-... | 08/21/2007 |
| 7253057 | Memory cell with reduced size and standby current A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers which allows a tunnel window of a storage device to be fabricat... | 08/07/2007 |
| 7220643 | System and method for gate formation in a semiconductor device A method for forming a memory device is provided. A memory cell stack is formed over a substrate. The memory cell stack includes a first layer formed over the substrate and a second layer formed over the first layer. A dielectric layer is formed over the first and s... | 05/22/2007 |
| 7186614 | Method for manufacturing high density flash memory and high performance logic on a single die A method of forming high performance logic transistors and high density flash transistors on a single substrate is disclosed. In one embodiment, the method comprises: forming a logic gate stack in a logic region on a substrate, forming a flash memory gate stack in a... | 03/06/2007 |
| 7183161 | Programming and erasing structure for a floating gate memory cell and method of making A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase ... | 02/27/2007 |
| 7183158 | Method of fabricating a non-volatile memory A method of fabricating a nonvolatile memory is provided. The method includes forming a bottom dielectric layer, a charge trapping layer, a top dielectric layer and a conductive layer on the substrate sequentially. Portions of conductive layer, top dielectric layer,... | 02/27/2007 |
| 7179709 | Method of fabricating non-volatile memory device having local SONOS gate structure in methods of fabricating a non-volatile memory device having a local silicon-oxide-nitride-oxide-silicon (SONOS) gate structure, a semiconductor substrate having a cell transistor area, a high voltage transistor area, and a low voltage transistor area, is prepared.... | 02/20/2007 |
| 7169672 | Split gate type nonvolatile memory device and manufacturing method thereof A method for fabricating a nonvolatile memory device comprises the steps of: defining an active region in a semiconductor substrate; forming a charge trapping layer, a first conducting layer and a capping layer on the active region; patterning the capping layer to f... | 01/30/2007 |
| 7148133 | Method of manufacturing flash memory device A method of manufacturing a flash memory device, including the steps of laminating a tunnel oxide film and a first polysilicon layer on a region of a semiconductor substrate, and forming isolation films having a step with a first polysilicon layer between the tunnel... | 12/12/2006 |
| 7141480 | Tri-gate low power device and method for manufacturing the same The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [... | 11/28/2006 |
| 7141474 | Fabrication method of a nonvolatile semiconductor memory A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor substrate; depositing an inter-gate insulating layer; forming an openin... | 11/28/2006 |
| 7136302 | Integrated circuit memory device and method Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the ch... | 11/14/2006 |
| 7122432 | Non-volatile semiconductor memory device and manufacturing method thereof A non-volatile semiconductor memory device with a small variation in capacitance-coupling to the stacked gate for memory miniaturization. The device has a memory cell array in which memory cells are arranged in array. Each cell has a first gate and a second gate on ... | 10/17/2006 |
| 7094645 | Programming and erasing structure for a floating gate memory cell and method of making A floating gate memory cell has a floating gate in which there are two adjacent floating gate layers. The top layer is made to have a contour while leaving the lower layer substantially unchanged. An interlevel dielectric and a control gate follow the contour of the... | 08/22/2006 |
| 7091549 | Programmable memory devices supported by semiconductor substrates The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tun... | 08/15/2006 |
| 7084454 | Nonvolatile integrated semiconductor memory A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel ... | 08/01/2006 |
| 7074672 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source ... | 07/11/2006 |
| 7071060 | EEPROM with split gate source side infection with sidewall spacers Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one emb... | 07/04/2006 |
| 7049652 | Pillar cell flash memory technology An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon fl... | 05/23/2006 |
