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| Number | Title | Issue Date |
| 8168524 | Non-volatile memory with erase gate on isolation zones The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or... | 05/01/2012 |
| 8088683 | Sequential deposition and anneal of a dielectic layer in a charge trapping memory device Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 | 01/03/2012 |
| 8043951 | Method of manufacturing a semiconductor device and semiconductor device obtainable therewith A method of manufacturing a semiconductor device on a substrate. The method may include forming a non-volatile memory in a memory area of the substrate. The forming non-volatile memory on a substrate may include formation in the memory area of a floating gate struct... | 10/25/2011 |
| 8003508 | Method of forming gate line of semiconductor device A method of forming a gate line of a semiconductor device, wherein when an etch process for forming a gate line is performed, a loading effect is improved, thereby enhancing the operating speed of a semiconductor device. According to a method of forming a gate line ... | 08/23/2011 |
| 7985670 | Method of forming U-shaped floating gate with a poly meta-stable polysilicon layer A method of realizing a flash floating poly gate using an MPS process can include forming a tunnel oxide layer on an active region of a semiconductor substrate; and then forming a first floating gate on and contacting the tunnel oxide layer; and then forming second ... | 07/26/2011 |
| 7902059 | Methods of forming void-free layers in openings of semiconductor substrates In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion... | 03/08/2011 |
| 7838407 | Method for protecting the gate of a transistor and corresponding integrated circuit A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed i... | 11/23/2010 |
| 7816245 | Method of forming semiconductor devices in which a cell gate pattern and a resistor pattern are formed of a same material A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first in... | 10/19/2010 |
| 7799670 | Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance w... | 09/21/2010 |
| 7700472 | Method of forming a gate of a semiconductor device A method of forming a gate of a semiconductor device includes providing a semiconductor substrate over which a first conductive layer, a dielectric layer and a second conductive layer are formed. The second conductive layer is patterned to expose a part of the diele... | 04/20/2010 |
| 7696076 | Method of fabricating flash memory device The present invention relates to a method of fabricating a flash memory device. In a method according to an aspect of the present invention, a first hard mask film is formed over a semiconductor laminate. A plurality of first hard mask patterns are formed by etching... | 04/13/2010 |
| 7569468 | Method for forming a floating gate memory with polysilicon local interconnects Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present inventio... | 08/04/2009 |
| 7524747 | Floating gate memory device and method of manufacturing the same Disclosed herein is a method of forming a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation (SA-STI) structure. First, a tunnel oxide layer is formed on a semiconductor substrate having a SA-STI structure. Next, a first flo... | 04/28/2009 |
| 7439167 | Nonvolatile semiconductor memory and manufacturing method thereof A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor ... | 10/21/2008 |
| 7439131 | Flash memory device having resistivity measurement pattern and method of forming the same A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the r... | 10/21/2008 |
| 7436019 | Non-volatile memory cells shaped to increase coupling to word lines A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also... | 10/14/2008 |
| 7435648 | Methods of trench and contact formation in memory cells Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of... | 10/14/2008 |
| 7432158 | Method for retaining nanocluster size and electrical characteristics during processing A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first p... | 10/07/2008 |
| 7429766 | Split gate type nonvolatile memory device In a split gate type nonvolatile memory device, a supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore po... | 09/30/2008 |
| 7429514 | Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a t... | 09/30/2008 |
| 7416935 | Method of manufacturing nonvolatile semiconductor memory device having adjacent selection transistors connected together A method of manufacturing a nonvolatile semiconductor memory device, including forming a gate insulating film, a first conductive layer providing floating gates and a mask, in that order, on a semiconductor substrate, forming a plurality of element-isolating regions... | 08/26/2008 |
| 7410871 | Split gate type flash memory device and method for manufacturing same A split gate type flash memory device and a method of manufacturing the split gate type flash memory device are disclosed. The split gate type flash memory device includes a silicon epitaxial layer formed in an active region of a bulk silicon substrate and a disturb... | 08/12/2008 |
| 7410857 | Semiconductor memory device and manufacturing method thereof After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is form... | 08/12/2008 |
| 7407856 | Method of manufacturing a memory device A method of manufacturing a memory device includes defining a field region and an active region in a substrate, forming a field oxide layer on the field region, forming an insulating layer on the active region, patterning the insulating layer to form first and secon... | 08/05/2008 |
| 7402493 | Method for forming non-volatile memory devices According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insul... | 07/22/2008 |
| 7400010 | Semiconductor device and method of manufacturing the same A semiconductor device including a semiconductor substrate having trenches oriented in a predetermined direction; a gate insulating film overlaying the semiconductor substrate interposed between the trenches; and floating gate electrodes formed on the gate insulatin... | 07/15/2008 |
| 7399673 | Method of forming a charge-trapping memory device In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are formed parallel to said word lines within said substrate. These subdivide diffusion regions adjacent to the wo... | 07/15/2008 |
| 7393745 | Method for fabricating self-aligned double layered silicon-metal nanocrystal memory element A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon dispose... | 07/01/2008 |
| 7390730 | Method of fabricating a body capacitor for SOI memory A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between th... | 06/24/2008 |
| 7391073 | Non-volatile memory structure and method of fabricating non-volatile memory A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer.... | 06/24/2008 |
| 7384843 | Method of fabricating flash memory device including control gate extensions A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating ... | 06/10/2008 |
| 7381615 | Methods for self-aligned trench filling with grown dielectric for high coupling ratio in semiconductor devices Methods for self-aligned trench filling to isolate active regions in high-density integrated circuits are provided. A deep, narrow trench is etched into a substrate between active regions. The trench is filled by growing a suitable dielectric such as silicon dioxide... | 06/03/2008 |
| 7378336 | Split poly-SiGe/poly-Si alloy gate stack A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer o... | 05/27/2008 |
| 7374995 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposi... | 05/20/2008 |
| 7371672 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes removing a low-resistivity metal film, conductive layer, third insulating film and an upper part of the electrode layer in a gate electrode isolation region with a gate forming pattern serving as a mask, form... | 05/13/2008 |
| 7371647 | Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nit... | 05/13/2008 |
| 7371638 | Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same A non-volatile memory cell includes a semiconductor substrate having a fin-shaped active region extending therefrom. A tunnel dielectric layer is provided, which extends on opposing sidewalls and an upper surface of the fin-shaped active region. A floating gate elec... | 05/13/2008 |
| 7368780 | Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each... | 05/06/2008 |
| 7361543 | Method of forming a nanocluster charge storage device An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control e... | 04/22/2008 |
| 7358576 | Word line structure with single-sided partially recessed gate structure A word line structure with a single-sided partially recessed gate structure. The word line structure includes a gate structure, a first gate spacer, and a second gate spacer. The gate structure includes a gate dielectric layer, a first gate layer, a second gate laye... | 04/15/2008 |
