Did You Know...
...that power steering was invented by independent inventor Francis W. Davis? As chief engineer in the 1920s of the truck division of the Pierce Arrow Motor Car Company, he saw how hard it was to steer heavy vehicles. So that he would be able to keep the profits from his future invention, Davis left his job, rented a small engineering shop in Waltham, Mass., and developed a hydraulic power steering system that led to power steering.
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| Number | Title | Issue Date |
| 7981785 | Method for manufacturing semiconductor device and plasma oxidation method A polysilicon electrode layer (103) (a first electrode layer) is formed by forming a polysilicon film on a gate oxide film (102) on a silicon wafer (101). A tungsten layer (105) (a second electrode layer) is formed on this polysilicon ele... | 07/19/2011 |
| 7892958 | Methods of fabricating semiconductor devices having transistors with different gate structures A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other tra... | 02/22/2011 |
| 7820537 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes forming a polysilicon layer, a barrier metal layer, and a conductive layer over a substrate, forming gate hard masks over the conductive layer, etching the conductive layer and the barrier metal layer using th... | 10/26/2010 |
| 7767568 | Phase change memory device and method of fabricating the same A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second... | 08/03/2010 |
| 7718521 | Semiconductor device and method for manufacturing the same There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS tra... | 05/18/2010 |
| 7611979 | Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate di... | 11/03/2009 |
| 7585755 | Method of fabricating non-volatile memory device A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lo... | 09/08/2009 |
| 7569465 | Use of voids between elements in semiconductor structures for isolation A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage ... | 08/04/2009 |
| 7459383 | Fabricating method of gate structure A gate structure comprising a substrate, a gate dielectric layer, a first conductive layer, a second conductive layer, a cap layer and a first insulating spacer is provided. The gate dielectric layer is disposed on the substrate. The first conductive layer is dispos... | 12/02/2008 |
| 7439167 | Nonvolatile semiconductor memory and manufacturing method thereof A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor ... | 10/21/2008 |
| 7355253 | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric fo... | 04/08/2008 |
| 7354827 | Transistor having asymmetric channel region, semiconductor device including the same, and method of fabricating semiconductor device including the same According to embodiments of the invention, a transistor includes a semiconductor substrate having an active region. A channel trench is disposed to cross the active region. A gate insulating layer covers an inner wall of the channel trench. A gate pattern is dispose... | 04/08/2008 |
| 7339211 | Semiconductor device and method for fabricating the same Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening ... | 03/04/2008 |
| 7338907 | Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the e... | 03/04/2008 |
| 7332433 | Methods of modulating the work functions of film layers Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where t... | 02/19/2008 |
| 7329581 | Field effect transistor (FET) devices and methods of manufacturing FET devices In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first openin... | 02/12/2008 |
| 7326634 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed o... | 02/05/2008 |
| 7316945 | Method of fabricating a fin field effect transistor in a semiconductor device A method for fabricating a fin FET in a semiconductor device. The method includes sequentially depositing first and second insulation films on a semiconductor substrate, etching the first and second insulation films using a first mask to form a trench, and depositin... | 01/08/2008 |
| 7314814 | Semiconductor devices and methods of fabricating the same Semiconductor devices and methods of fabricating the same are disclosed. A disclosed method comprises: partially forming a first gate stack; partially forming a second gate stack adjacent the first gate stack; forming a first interlayer dielectric; and completing th... | 01/01/2008 |
| 7306990 | Information storage element, manufacturing method thereof, and memory array An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavi... | 12/11/2007 |
| 7300886 | Interlayer dielectric for charge loss improvement A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and ... | 11/27/2007 |
| 7291527 | Work function control of metals Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first... | 11/06/2007 |
| 7285815 | EEPROM device having selecting transistors and method of fabricating the same An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control ga... | 10/23/2007 |
| 7265007 | Method for fabricating field-effect transistor structures with gate electrodes with a metal layer Provided is a method for fabricating gate electrode structures each having at least one individual polysilicon layer and a metal layer. A polysilicon layer is provided and patterned prior to the application of the gate metal. Trenches between the resulting gate stru... | 09/04/2007 |
| 7259071 | Semiconductor device with dual gate oxides A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and... | 08/21/2007 |
| 7229889 | Methods for metal plating of gate conductors and semiconductors formed thereby A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one ... | 06/12/2007 |
| 7226851 | Method for manufacturing semiconductor device and non-volatile memory A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed... | 06/05/2007 |
| 7211866 | Scalable self-aligned dual floating gate memory cell array and methods of forming the array An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then ... | 05/01/2007 |
| 7208375 | Semiconductor device A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than th... | 04/24/2007 |
| 7202149 | Semiconductor device and manufacturing method thereof A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over ... | 04/10/2007 |
| 7202150 | Semiconductor memory device and manufacturing method therefor A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of se... | 04/10/2007 |
| 7183185 | Methods of forming transistor gates; and methods of forming programmable read-only memory constructions The invention includes a method of forming a transistor gate. One or more conductive materials are formed over a semiconductor substrate, and a block is formed over the one or more conductive materials. The block comprises a photoresist mass and a material other tha... | 02/27/2007 |
| 7180134 | Methods and structures for planar and multiple-gate transistors formed on SOI A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of th... | 02/20/2007 |
| 7179709 | Method of fabricating non-volatile memory device having local SONOS gate structure in methods of fabricating a non-volatile memory device having a local silicon-oxide-nitride-oxide-silicon (SONOS) gate structure, a semiconductor substrate having a cell transistor area, a high voltage transistor area, and a low voltage transistor area, is prepared.... | 02/20/2007 |
| 7176090 | Method for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider... | 02/13/2007 |
| 7160793 | Edge termination in MOS transistors A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known dev... | 01/09/2007 |
| 7157768 | Non-volatile flash semiconductor memory and fabrication method In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two... | 01/02/2007 |
| 7151023 | Metal gate MOSFET by full semiconductor metal alloy conversion A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to parti... | 12/19/2006 |
| 7125807 | Method for manufacturing non-volatile memory cells on a semiconductor substrate A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining ... | 10/24/2006 |
| 7125808 | Method for manufacturing non-volatile memory cells on a semiconductor substrate A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plura... | 10/24/2006 |
