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| Number | Title | Issue Date |
| 7858506 | Diodes, and methods of forming diodes Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrod... | 12/28/2010 |
| 7811917 | Systems and methods for maintaining performance at a reduced power Systems and methods are provided for maintaining performance of an integrated circuit at a reduced power. The systems and methods employ a performance monitor that generates a signal indicative of at least one performance characteristic of at least a portion of a cr... | 10/12/2010 |
| 7772101 | Phase-change memory device and method for manufacturing the same A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-... | 08/10/2010 |
| 7365384 | Trench buried bit line memory devices and methods thereof A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermo... | 04/29/2008 |
| 7351088 | Electrical connector with self-locking by snap-fastening An electrical connector, a ring-like locking sheet with inner and outer teeth of which is fixed at the end of its plug connector; and a circumferential bulge, with trapezoid cross section which has an upslope, a flat top and a down-slope, is provided on the surface ... | 04/01/2008 |
| 7253671 | Apparatus and method for compensating for clock drift in downhole drilling components A precise downhole clock that compensates for drift includes a prescaler configured to receive electrical pulses from an oscillator. The prescaler is configured to output a series of clock pulses. The prescaler outputs each clock pulse after counting a preloaded num... | 08/07/2007 |
| 7229847 | Forming electrical contacts to a molecular layer The present invention provides a process for forming electrical contacts to a molecular layer in a nanoscale device, the nanoscale device, and a method of manufacturing an integrated circuit comprise such devices. The process includes coating a surface of a stamp wi... | 06/12/2007 |
| 7166894 | Schottky power diode with SiCOI substrate and process for making such diode The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky con... | 01/23/2007 |
| 7005302 | Semiconductor on insulator substrate and devices formed therefrom A semiconductor on insulator (SOI) device is comprised of a layer of a dielectric material having a perovskite lattice, such as a rare earth scandate. The dielectric material is selected to have an effective lattice constant that enables growth of semiconductor mate... | 02/28/2006 |
| 7002187 | Integrated schottky diode using buried power buss structure and method for making same An integrated Schottky diode and method of manufacture of such a diode is disclosed. In a first aspect, a Schottky diode comprises a semiconductor substrate. The semiconductor substrate includes an epitaxial layer (EPI) on the substrate region. The diode includes a ... | 02/21/2006 |
| 6987289 | High-density FinFET integration scheme The invention provides a method of manufacturing a fin-type field effect transistor (FinFET) that forms a unique FinFET that has a first fin with a central channel region and source and drain regions adjacent the channel region, a gate intersecting the first fin and... | 01/17/2006 |
| 6884669 | Hatted polysilicon gate structure for improving salicide performance and method of forming the same Alternate methods of forming low resistance “hatted” polysilicon gate elements are provided that increase the effective area in the polysilicon gate for silicide grain growth during silicide formation. The expanded top portion helps to prevent silicide agglomera... | 04/26/2005 |
| 6825105 | Manufacture of semiconductor devices with Schottky barriers In the manufacture of trench-gate power MOSFETs, trenched Schottky rectifiers and other devices including a Schottky barrier, a guard region (15s), trenched insulated electrode (11s) and the Schottky barrier (80) are self-aligned w... | 11/30/2004 |
| 6815347 | Method of forming a reflective electrode The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applie... | 11/09/2004 |
| 6790753 | Field plated schottky diode and method of fabrication therefor A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over... | 09/14/2004 |
| 6784036 | Method for making semiconductor device A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a ... | 08/31/2004 |
| 6764966 | Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the se... | 07/20/2004 |
| 6737305 | Thin film transistor manufacture method A Thin Film Transistor (TFT) manufacture method, comprising manufacture of a gate, a gate isolation layer, a channel layer, and a source/drain. Wherein, the manufacture of the channel layer comprises: forming a first a-Si layer by using a low deposition rate (LDR) (... | 05/18/2004 |
| 6667215 | Method of making transistors A method for making transistors comprises depositing source electrode and drain electrode features onto a substrate through a single aperture in a stationary shadow mask, said aperture having at least two opposing edges; wherein the shapes of the features... | 12/23/2003 |
| 6620655 | Array substrate for transflective LCD device and method of fabricating the same An array substrate for a transflective liquid crystal display device, including a substrate; at least one gate line and at least one gate electrode formed on the transparent substrate; a gate-insulating layer formed over the at least one gate line and the... | 09/16/2003 |
| 6613662 | Method for making projected contact structures for engaging bumped semiconductor devices A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a ... | 09/02/2003 |
| 6541340 | Method of manufacturing a semiconductor device with a concave trench A semiconductor device and a method of manufacturing the same are provided which are novel and fully improved and are capable of lowering satisfactorily a high-frequency resistance or direct current resistance in a signal line. The semiconductor device is... | 04/01/2003 |
| 6475890 | Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface and first and second... | 11/05/2002 |
| 6455405 | Using implantation method to control gate oxide thickness on dual oxide semiconductor devices A method for forming dual thickness gate oxide layers comprising the following steps. A structure having at least a first area and a second area is provided. The second area of the structure is masked. Ion implanting Si4+ or Ge4+ ion... | 09/24/2002 |
| 6403456 | T or T/Y gate formation using trim etch processing A method for fabricating a T-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second ... | 06/11/2002 |
| 6372613 | Method of manufacturing a gate electrode with low resistance metal layer remote from a semiconductor In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertica... | 04/16/2002 |
| 6268662 | Wire bonded flip-chip assembly of semiconductor devices A semiconductor assembly comprising a semiconductor chip having an active and a passive surface, said active surface including an integrated circuit and a plurality of bonding pads; said bonding pads having a metallization suitable for wire bonding; an ar... | 07/31/2001 |
| 6204102 | Method of fabricating compound semiconductor devices using lift-off of insulating film A method of forming a gate electrode of a compound semiconductor device includes forming a first insulating film pattern having a first aperture, forming a second insulating film pattern having a second aperture consisting of inverse V-type on the first i... | 03/20/2001 |
| 6177326 | Method to form bottom electrode of capacitor A method for fabricating a bottom electrode is provided. In this method a dielectric layer is formed on a substrate having a source/drain region. A via hole is formed in the dielectric layer to expose the source/drain region. A patterned, doped polysilico... | 01/23/2001 |
| 6139922 | Tantalum and tantalum-based films formed using fluorine-containing source precursors and methods of making the same A method for chemical vapor deposition of a film comprising tantalum onto a substrate includes introducing into a deposition chamber: (i) a substrate; (ii) a source precursor in the vapor state; and (iii) a reactant gas, and maintaining the temperature of... | 10/31/2000 |
| 6100172 | Method for forming a horizontal surface spacer and devices formed thereby The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an impl... | 08/08/2000 |
| 6096644 | Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and metal silicides Self-aligned contacts to the source and drain regions of a MOS device are formed by selectively removing portions of sidewall spacers from polysilicon source and drain electrodes. Metal silicide layers are then formed in contact with the exposed polysilic... | 08/01/2000 |
| 6077761 | Method for fabricating a transistor gate with a T-like structure A method for fabricating a field effect transistor (FET) with a T-like gate structure includes forming a silicon nitride layer over a silicon substrate and patterning it to form an opening that exposes the substrate. A dielectric layer is formed on a lowe... | 06/20/2000 |
| 5925902 | Semiconductor device having a schottky film with a vertical gap formed therein In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertica... | 07/20/1999 |
| 5652179 | Method of fabricating sub-micron gate electrode by angle and direct evaporation Disclosed is a method of fabricating semiconductor devices having sub-micron gate electrodes using angle and direct evaporation techniques. A first and second photoresist layer are formed atop a substrate and the second layer is selectively processed to f... | 07/29/1997 |
| 5610090 | Method of making a FET having a recessed gate structure A Field Effect Transistor having a recessed gate comprises a substrate, a source electrode and a drain electrode, a recessed channel region formed over an area of the semiconductor substrate between the source electrode and the drain electrode, and a gate... | 03/11/1997 |
| 5538910 | Method of making a narrow gate electrode for a field effect transistor A method of producing a field effect transistor that includes forming a step in a compound semiconductor substrate, forming a first insulating side wall at the step, forming an etch blocking layer on the substrate, removing the first insulating side wall,... | 07/23/1996 |
| 5486483 | Method of forming closely spaced metal electrodes in a semiconductor device A method of forming closely spaced metal electrodes contacting different regions of a semiconductor device is disclosed. The method includes first depositing a sacrificial layer over a developing semiconductor structure. Next, a photoresist layer is depos... | 01/23/1996 |
| 5470767 | Method of making field effect transistor A semiconductor device having a gate electrode having a leg with two mutually offset portions is formed by successively depositing on a semiconductor substrate an amorphous material and a crystalline metal layer. A portion of the crystalline metal layer i... | 11/28/1995 |
| 5432126 | Fabrication process of compound semiconductor device comprising L-shaped gate electrode After forming a silicon oxide layer and an amorphous silicon layer on a GaAs substrate in stacking manner, a gate electrode forming opening portion is formed by RIE etching. Then, by selectively removing only the amorphous silicon layer at the portion con... | 07/11/1995 |
