Class 438/576 - Into grooved or recessed semiconductor region

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes wherein the contact is formed in a recess in the
No. of patents: 91
Last issue date: 11/01/2011

«First «Previous1 2 3 Next»Last»

Number	Title	Issue Date
8048789	Mesoscale pyramids, arrays and methods of preparation Ordered, two-dimensional arrays of pyramidal particulates and related methods of preparation. ...	11/01/2011
7829448	Structure of high electron mobility transistor, a device comprising the structure and a method of producing the same Disclosed herein are a structure of a metal oxide semiconductor pseudomorphic high electron mobility transistor (MOS-PHEMT) suitable for use in a semiconductor device, such as a single-pole-double-throw (SPDT) switch of a monolithic microwave integrated circuit (MMI...	11/09/2010
7655546	Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. ...	02/02/2010
7429523	Method of forming schottky diode with charge balance structure a Schottky diode having a semiconductor region is formed as follows. A plurality of charge control electrodes are formed in the semiconductor region so as to influence an electric field in the semiconductor region, wherein at least two of the charge control electrod...	09/30/2008
7375019	Image sensor and method for fabricating the same An image sensor and a method for fabricating the same are disclosed, to improve a contact quality between a contact plug and a source diffusion layer. The image sensor includes a photodiode in an active area of a semiconductor substrate, for receiving incident exter...	05/20/2008
7365384	Trench buried bit line memory devices and methods thereof A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermo...	04/29/2008
7323402	Trench Schottky barrier diode with differential oxide thickness A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination...	01/29/2008
7262134	Microfeature workpieces and methods for forming interconnects in microfeature workpieces Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a t...	08/28/2007
7229903	Recessed semiconductor device A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A f...	06/12/2007
7193324	Circuit structure of package substrate A circuit structure for a package substrate or a circuit board is provided. The circuit structure has a dielectric layer with an upper surface and a lower surface, at least a first line and at least a second line. The first line is disposed on the dielectric layer o...	03/20/2007
7172933	Recessed polysilicon gate structure for a strained silicon MOSFET device A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate...	02/06/2007
7098113	Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor...	08/29/2006
7074623	Methods of forming strained-semiconductor-on-insulator finFET device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ...	07/11/2006
7002187	Integrated schottky diode using buried power buss structure and method for making same An integrated Schottky diode and method of manufacture of such a diode is disclosed. In a first aspect, a Schottky diode comprises a semiconductor substrate. The semiconductor substrate includes an epitaxial layer (EPI) on the substrate region. The diode includes a ...	02/21/2006
6921957	Low forward voltage drop schottky barrier diode and manufacturing method therefor A new low forward voltage drop Schottky barrier diode and its manufacturing method are provided. The method includes steps of providing a substrate, forming plural trenches on the substrate, and forming a metal layer on the substrate having plural trenches thereon t...	07/26/2005
6887747	Method of forming a MISFET having a schottky junctioned silicide There is disclosed a semiconductor device in which a device isolating insulating film is formed in a periphery of a device region of a semiconductor silicon substrate device region. A side wall insulating film formed of a silicon nitride film is formed to cover the ...	05/03/2005
6864145	Method of fabricating a robust gate dielectric using a replacement gate flow A method is described for selectively treating the properties of a gate dielectric near corners of the gate without altering the gate dielectric in a center region of a gate channel. The method includes providing a structure having a gate opening and depositing a la...	03/08/2005
6855593	Trench Schottky barrier diode A fabrication process for a Schottky barrier structure includes forming a nitride layer directly on a surface of an epitaxial (“epi”) layer and subsequently forming a plurality of trenches in the epi layer. The interior walls of the trenches are then deposited w...	02/15/2005
6825105	Manufacture of semiconductor devices with Schottky barriers In the manufacture of trench-gate power MOSFETs, trenched Schottky rectifiers and other devices including a Schottky barrier, a guard region (15s), trenched insulated electrode (11s) and the Schottky barrier (80) are self-aligned w...	11/30/2004
6825073	Schottky diode with high field breakdown and low reverse leakage current A Schottky diode structure and a method of making the same are disclosed. The method comprises following steps: firstly, a semiconductor substrate having a first conductive layer and an epi-layer doped with the same type impurities is provided. Then a first oxide la...	11/30/2004
6770548	Trench schottky rectifier A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of ...	08/03/2004
6762098	Trench DMOS transistor with embedded trench schottky rectifier An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit comprises: (a) a substrate of a first conduct...	07/13/2004
6740951	Two-mask trench schottky diode A Schottky rectifier includes a semiconductor structure having first and second opposing faces each extending to define an active semiconductor region and a termination semiconductor region. The semiconductor structure includes a cathode region of the first conducti...	05/25/2004
6649497	Method of forming vias in silicon carbide and resulting devices and circuits A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon ca...	11/18/2003
6593620	Trench DMOS transistor with embedded trench schottky rectifier An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit includes: (a) a substrate of a fir...	07/15/2003
6576973	Schottky diode on a silicon carbide substrate A vertical Schottky diode including an N-type silicon carbide layer of low doping level formed by epitaxy on a silicon carbide substrate of high doping level. The periphery of the active area of the diode is coated with a P-type epitaxial silicon carbide ...	06/10/2003
6573129	Gate electrode formation in double-recessed transistor by two-step etching A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of Gax In1-x As is disposed below the source electrode and the drain electrode and provides a cap layer opening. An un...	06/03/2003
6518152	Method of forming a trench schottky rectifier A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift...	02/11/2003
6509234	Method of fabricating an ultra-thin fully depleted SOI device with T-shaped gate A method of forming a fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET). The method includes forming a T-shaped gate electrode formed at least in part in a recess formed in a layer of semiconductor material and over a body regi...	01/21/2003
6475890	Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface and first and second...	11/05/2002
6455403	Shallow trench contact structure to solve the problem of schottky diode leakage A method for fabricating a Schottky diode using a shallow trench contact to reduce leakage current in the fabrication of an integrated circuit device is described. The method provides a simple and effective method for decreasing the possibility of forming...	09/24/2002
6417035	Method for manufacturing a field effect transistor It is an object of the invention to solve a problem that a gate breakdown voltage and RF characteristics of a field effect transistor, which is provided with a double recess composed of a wide recess and a narrow recess, is not satisfactory. This problem ...	07/09/2002
6395588	Compound semiconductor device and method of manufacturing the same The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1~1016 to 1~1017 atoms/cm3, or the bandgap of a Schottky layer is set w...	05/28/2002
6316302	Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of re...	11/13/2001
6307221	InxGa1-xP etch stop layer for double recess pseudomorphic high electron mobility transistor structures The invention is a Pseudomorphic transistor structure having a semiconductor layer having a 2DEG layer therein, a Schottky layer, a transition layer and an ohmic contact layer on the transition layer, wherein a double recess structure is disposed through ...	10/23/2001
6242293	Process for fabricating double recess pseudomorphic high electron mobility transistor structures The invention is a method for fabricating a pseudomorphic HEMT transistor structure with a semiconductor layer having a 2DEG layer therein, a Schottky layer, a transition layer, and an ohmic contact layer on the transition layer. A double recess structure...	06/05/2001
6218688	Schottky diode with reduced size The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is ...	04/17/2001
6204102	Method of fabricating compound semiconductor devices using lift-off of insulating film A method of forming a gate electrode of a compound semiconductor device includes forming a first insulating film pattern having a first aperture, forming a second insulating film pattern having a second aperture consisting of inverse V-type on the first i...	03/20/2001
6180440	Method of fabricating a recessed-gate FET without producing voids in the gate metal The present invention provides a method of fabricating a field-effect transistor comprising the steps of forming a masking layer having an opening therein on laminated compound semiconductor layers, removing a portion of the laminated layers using an etch...	01/30/2001
6165826	Transistor with low resistance tip and method of fabrication in a CMOS process A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first ga...	12/26/2000

«First «Previous1 2 3 Next»Last»

PatentStorm

Bizarre Patents

PatentStorm News

Class 438/576 - Into grooved or recessed semiconductor region