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| Number | Title | Issue Date |
| 8163633 | Light-emitting nanoparticles and method of making same A method for the production of a robust, chemically stable, crystalline, passivated nanoparticle and composition containing the same, that emit light with high efficiencies and size-tunable and excitation energy tunable color. The methods include the thermal degrada... | 04/24/2012 |
| 8148246 | Method for separating semiconductor layer from substrate A method for separating a semiconductor from a substrate is disclosed. The method comprises the following steps: forming a plurality of columns on a substrate; epitaxially growing a semiconductor on the plurality of columns; and injecting etching liquid into the voi... | 04/03/2012 |
| 8021967 | Nanoscale wicking methods and devices A fluid transport method and fluid transport device are disclosed. Nanoscale fibers disposed in a patterned configuration allow transport of a fluid in absence of an external power source. The device may include two or more fluid transport components having differen... | 09/20/2011 |
| 7888248 | Method of producing large area SiC substrates A method for growing a SiC-containing film on a Si substrate is disclosed. The SiC-containing film can be formed on a Si substrate by, for example, plasma sputtering, chemical vapor deposition, or atomic layer deposition. The thus-grown SiC-containing film provides ... | 02/15/2011 |
| 7452792 | Relaxation of layers The invention relates to a method of forming a layer of elastically unstrained crystalline material intended for electronics, optics, or optronics applications, wherein the method is carried out using a structure that includes a first crystalline layer which is elas... | 11/18/2008 |
| 7432132 | Integrated diamond carrier method for laser bar arrays A method of making efficient Integrated Diamond Carrier heat sink and mounting structures usable typically to mount the solid-state laser bars often employed for pumping high power lasers, for example. The disclosed method forms the Integrated Diamond Carrier on a s... | 10/07/2008 |
| 7416965 | Method for producing a strained layer on a substrate and corresponding layer structure The invention relates to a method for producing a layer structure comprising a strained layer on a substrate. The inventive method comprises the steps of producing a defect area in a layer adjoining the layer to be strained, and relaxing at least one layer adjoining... | 08/26/2008 |
| 7405140 | Low temperature formation of patterned epitaxial Si containing films A method for selectively forming an epitaxial Si containing film on a semiconductor structure at low temperature. The method includes providing the structure in a process chamber, the structure containing a Si substrate having an epitaxial Si surface area and a patt... | 07/29/2008 |
| 7375011 | Ex-situ doped semiconductor transport layer A method of making an ex-situ doped semiconductor transport layer for use in an electronic device includes: growing a first set of semiconductor nanoparticles having surface organic ligands in a colloidal solution; growing a second set of dopant material nanoparticl... | 05/20/2008 |
| 7361563 | Methods of fabricating a semiconductor device using a selective epitaxial growth technique Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are... | 04/22/2008 |
| 7332746 | Light-emitting apparatus A novel configuration of a light-emitting apparatus that can emit white light, in which a primary light source composed of a group III nitride compound semiconductor is used in combination with a secondary light source including a fluorescent material which emits li... | 02/19/2008 |
| 7329593 | Germanium deposition A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 Å. The method further comprises, after depositing th... | 02/12/2008 |
| 7330088 | Waveguide orthomode transducer A waveguide orthomode transducer includes a first radio wave conducting means for conducting an electric wave of a horizontally polarized wave branched by an electric wave branch means, for conducting another electric wave of the horizontally polarized wave, for com... | 02/12/2008 |
| 7327036 | Method for depositing a group III-nitride material on a silicon substrate and device therefor The present invention is related to a device comprising a substrate comprising a silicon substrate having a porous top layer, a second layer on said top layer, said second layer made of a material comprising Ge, and a further layer of a Group III-nitride material on... | 02/05/2008 |
| 7294520 | Method for fabricating a plurality of semiconductor bodies, and electronic semiconductor body A method for fabricating a plurality of semiconductor bodies, in particular based on nitride compound semiconductor material. The method includes forming a mask layer (3) over a substrate (1) or over an initial layer (2), which mask layer has a ... | 11/13/2007 |
| 7285196 | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requir... | 10/23/2007 |
| 7279377 | Method and structure for shallow trench isolation during integrated circuit device manufacture A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises etching through silicon nitride and pad oxide layers and into a semiconductor wafer to form a trench into... | 10/09/2007 |
| 7262117 | Germanium integrated CMOS wafer and method for manufacturing the same The present invention discloses an integration flow of germanium into a conventional CMOS process, with improvements in performing selective area growth, and implementing electrical contacts to the germanium, in a way that has minimal impact on the preexisting trans... | 08/28/2007 |
| 7262505 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on... | 08/28/2007 |
| 7247535 | Source/drain extensions having highly activated and extremely abrupt junctions A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the ... | 07/24/2007 |
| 7247952 | Optical targets An optical target is provided. In one embodiment, the target is formed on a substrate. The target includes a first layer deposited below a second layer on the substrate. The second layer is deposited below a third layer on the substrate. The first layer has a topogr... | 07/24/2007 |
| 7235818 | Flip chip type nitride semiconductor light emitting device and manufacturing method thereof Disclosed herein are a flip chip type nitride semiconductor light emitting device, which comprises a substrate for growing a nitride semiconductor material, an n-type nitride semiconductor layer formed on the substrate, an active layer formed on at least a part of t... | 06/26/2007 |
| 7233065 | Semiconductor device having capacitors for reducing power source noise A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconducto... | 06/19/2007 |
| 7230315 | Integrated chemical microreactor with large area channels and manufacturing process thereof The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the chan... | 06/12/2007 |
| 7198671 | Layered substrates for epitaxial processing, and device A substrate comprising at least two layers which have different thermal expansion coefficients (TECs) is used for subsequent epitaxial growth of semiconductors. A typical example is an epitaxial growth of III-V Nitride (InGaAlBNAsP alloy semiconductor) on sapphire. ... | 04/03/2007 |
| 7198970 | Technique for perfecting the active regions of wide bandgap semiconductor nitride devices This invention pertains to electronic/optoelectronic devices with reduced extended defects and to a method for making it. The method includes the steps of depositing a dielectric thin film mask material on a semiconductor substrate surface; patterning the mask mater... | 04/03/2007 |
| 7192849 | Methods of growing nitride-based film using varying pulses Nitride-based film is grown using multiple precursor fluxes. Each precursor flux is pulsed one or more times to add a desired element to the nitride-based film at a desired time. The quantity, duration, timing, and/or shape of the pulses is customized for each eleme... | 03/20/2007 |
| 7183179 | System and method for hydrogen exfoliation gettering A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a ... | 02/27/2007 |
| 7179727 | Formation of lattice-tuning semiconductor substrates A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining parallel strips of a Si surface by the provision of spaced parallel oxide walls (2) on the surface, selectively growing a first SiGe layer on the strips such that fir... | 02/20/2007 |
| 7179728 | Optical component and manufacturing method thereof, microlens substrate and manufacturing method thereof, display device, and imaging device The invention provides an optical component whose siting, shape and size are well controlled and a method of manufacturing such an optical component. The optical component of the present invention includes a base member disposed on a substrate, and an optical member... | 02/20/2007 |
| 7170095 | Semi-insulating GaN and method of making the same Large-area, single crystal semi-insulating gallium nitride that is usefully employed to form substrates for fabricating GaN devices for electronic and/or optoelectronic applications. The large-area, semi-insulating gallium nitride is readily formed by doping the gro... | 01/30/2007 |
| 7166493 | Package with integrated inductor and/or capacitor Methods for attaching two wafers are presented along with devices resulting from such methods. In one illustrative embodiment, a first wafer is provided having pillars for conducting an electric signal. The wafer also includes an electronic device such as an inducto... | 01/23/2007 |
| 7148121 | Semiconductor on insulator device architecture and method of construction An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14 is used to provide a cohesive bond with a buried insulator layer 18. The sem... | 12/12/2006 |
| 7135420 | Semiconductor device and manufacturing method thereof Single crystal silicon is grown in a [100] direction to make a bulk. Next, a silicon substrate with a normal of a surface extending in an inclined direction from a [100] direction is cut from the bulk. At this time, when an angle (off-angle) of inclination of the no... | 11/14/2006 |
| 7112882 | Structures and methods for heat dissipation of semiconductor integrated circuits Structures and methods for semiconductor integrated circuits with respect to heat dissipation are provided. The structure comprises a die having a first surface and a second surface. The first surface has an opening in it, and the second surface has a contact pad fo... | 09/26/2006 |
| 7109099 | End of range (EOR) secondary defect engineering using substitutional carbon doping A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer... | 09/19/2006 |
| 7091611 | Multilevel copper interconnects with low-k dielectrics and air gaps Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which ... | 08/15/2006 |
| 7084046 | Method of fabricating SOI wafer After completion of annealing for bonding of the base wafer 1 and bond wafer 2, the bond wafer 2 is thinned to a first thickness suitable for ion implantation, and boron is ion-implanted to thereby form a high-boron-concentration layer 10... | 08/01/2006 |
| 7071548 | Semiconductor coated with a mixture containing an adhesion promoter An article comprises a semiconductor substrate and a coating mixture on the semiconductor substrate. The coating mixture Is comprised of adhesion promoter and photopolymer. The adhesion promoter contains α-amino propyltriethoxysilane in organic solution. ... | 07/04/2006 |
| 7067421 | Multilevel copper interconnect with double passivation Structures and methods provide multilevel wiring interconnects in an integrated circuit assembly which alleviate problems associated with integrated circuit size and performance and include methods for forming multilevel wiring interconnects in an integrated circuit... | 06/27/2006 |
