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Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
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| Number | Title | Issue Date |
| 8183133 | Method for producing semiconductor substrate There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having no oxide film wherein hydrogen ions are implanted into a wafer for active layer having no oxide film on its surface to form a hydrogen i... | 05/22/2012 |
| 8163632 | Irradiation with high energy ions for surface structuring and treatment of surface proximal sections of optical elements A method for processing the surface of a component, or the processing of an optical element through an ion beam, directed onto the surface to be processed, so that the surface is lowered and/or removed at least partially, wherein the ions have a kinetic energy of 10... | 04/24/2012 |
| 8034695 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device comprising the steps of: forming a first silicon oxide film which covers a first region on the top surface of a silicon substrate, but which does not cover a second region and a third region thereon; oxidizing the sil... | 10/11/2011 |
| 8030187 | Method for manufacturing semiconductor device A substrate is exposed to a plasma generated from a gas containing an impurity, thereby doping a surface portion of the substrate with the impurity and thus forming an impurity region. A predetermined plasma doping time is used, which is included within a time range... | 10/04/2011 |
| 7927980 | Method for forming a detachable substrate including implantation and exfoliation The invention concerns a method for forming a growth mask on the surface of an initial crystalline substrate, comprising the following steps: formation of a layer of second material on one of the faces of the initial substrate of f... | 04/19/2011 |
| 7915149 | Gallium nitride substrate and gallium nitride layer formation method There is disclosed a method for forming a gallium nitride layer of which resistivity is 1×106 Ω·cm or more, including steps of: forming a gallium nitride layer containing iron on a substrate; and heating said gallium nitride layer formed on said substr... | 03/29/2011 |
| 7910463 | Method of producing SIMOX wafer A SIMOX wafer is produced by implanting an oxygen ion, in which a hydrogen ion is implanted at a dose of 1015-1017/cm2 before or after the step of the oxygen ion implantation. ... | 03/22/2011 |
| 7892951 | SOI substrates with a fine buried insulating layer A method of producing a semiconductor structure having a buried insulating layer having a thickness between 2 and 25 nm, by: forming at least one insulating layer on a surface of a first or second substrate, or both, wherein the surfaces are free from an insulator o... | 02/22/2011 |
| 7879699 | Wafer and a method for manufacturing a wafer A wafer includes a wafer frontside and a region adjacent to the device surface, wherein the region includes vacancy-oxygen complexes and the wafer frontside includes a predetermined surface structure to form thereon a device with a desired property. ... | 02/01/2011 |
| 7851337 | Method for producing semiconductor substrate There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having no oxide film wherein hydrogen ions are implanted into a wafer for active layer having no oxide film on its surface to form a hydrogen i... | 12/14/2010 |
| 7659184 | Plasma immersion ion implantation process with chamber seasoning and seasoning layer plasma discharging for wafer dechucking In a plasma immersion ion implantation process, the thickness of a pre-implant chamber seasoning layer is increased (to permit implantation of a succession of wafers without replacing the seasoning layer) without loss of wafer clamping electrostatic force due to inc... | 02/09/2010 |
| 7442586 | SOI substrate and SOI device, and method for forming the same An improved semiconductor-on-insulator (SOI) substrate is provided, which has a substantially planar upper surface and comprises at least first and second patterned buried insulator layers. Specifically, the first patterned buried insulator layer has a first thickne... | 10/28/2008 |
| 7439092 | Thin film splitting method A method of fabricating thin films of semiconductor materials by implanting ions in a substrate composed of at least two different elements at least one of which can form a gaseous phase on bonding with itself and/or with impurities includes the following steps: | 10/21/2008 |
| 7432122 | Electronic device and a process for forming the electronic device An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive me... | 10/07/2008 |
| 7375035 | Host and ancillary tool interface methodology for distributed processing A host and ancillary tool interface methodology for distributed processing is described. The host tool manages a process, except for the generation of a product used in the process. To generate the product, the host tool provides an indication to an ancillary tool t... | 05/20/2008 |
| 7354786 | Sensor element with trenched cavity A micromechanical sensor element and a method for the production of a micromechanical sensor element that is suitable, for example in a micromechanical component, for detecting a physical quantity. Provision is made for the sensor element to include a substrate, an ... | 04/08/2008 |
| 7352034 | Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be inte... | 04/01/2008 |
| 7348610 | Multiple layer and crystal plane orientation semiconductor substrate A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline... | 03/25/2008 |
| 7348253 | High-quality SGOI by annealing near the alloy melting point A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant ... | 03/25/2008 |
| 7335611 | Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer A method of forming a conductor in a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on... | 02/26/2008 |
| 7323401 | Semiconductor substrate process using a low temperature deposited carbon-containing hard mask A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern... | 01/29/2008 |
| 7312148 | Copper barrier reflow process employing high speed optical annealing A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier met... | 12/25/2007 |
| 7312162 | Low temperature plasma deposition process for carbon layer deposition A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone... | 12/25/2007 |
| 7304328 | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The fir... | 12/04/2007 |
| 7294563 | Semiconductor on insulator vertical transistor fabrication and doping process A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conform... | 11/13/2007 |
| 7291545 | Plasma immersion ion implantation process using a capacitively couple plasma source having low dissociation and low minimum plasma voltage A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking... | 11/06/2007 |
| 7291538 | Semiconductor memory device and manufacturing method of the same In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region,... | 11/06/2007 |
| 7291360 | Chemical vapor deposition plasma process using plural ion shower grids A chemical vapor deposition process is carried out in a reactor chamber having a set of plural parallel ion shower grids that divide the chamber into an upper ion generation region and a lower process region, each of the ion shower grids having plural orifices in mu... | 11/06/2007 |
| 7288491 | Plasma immersion ion implantation process One method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber includes initially depositing a seasoning film on the interior surfaces of the plasma reactor chamber before the workpiece is introduced, by introducing a seasoning... | 10/30/2007 |
| 7285480 | Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FE... | 10/23/2007 |
| 7278903 | Processing method for wafer and processing apparatus therefor A processing method for wafers includes: a preparing step for preparing a wafer having an active device region and a reinforcing rib region. The active device region having plural devices is formed on a surface of the wafer, and the reinforcing rib region is at an o... | 10/09/2007 |
| 7273788 | Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to... | 09/25/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7268646 | Temperature controlled MEMS resonator and method for controlling resonator frequency There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a temperature compensated microelectromechanical resonator as well as fabricating, manufacturing, providing and/or controlling microelectromechanical reso... | 09/11/2007 |
| 7262428 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 08/28/2007 |
| 7260797 | Method and apparatus for estimating parasitic capacitance One embodiment of the present invention provides a system for estimating parasitic capacitance for an integrated circuit. During operation, the system reads a technology file, which describes the composition of a vertical cross-section of the integrated circuit. Nex... | 08/21/2007 |
| 7259053 | Methods for forming a device isolation structure in a semiconductor device Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material... | 08/21/2007 |
| 7247569 | Ultra-thin Si MOSFET device structure and method of manufacture The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a ... | 07/24/2007 |
| 7244474 | Chemical vapor deposition plasma process using an ion shower grid A chemical vapor deposition process is carried out in a reactor chamber with an ion shower grid that divides the chamber into an upper ion generation region and a lower process region, the ion shower grid having plural orifices oriented in a non-parallel direction r... | 07/17/2007 |
| 7235857 | Power semiconductor device A semiconductor device is provided in which a plurality of MOSFETs including a vertical MOSFET is formed on a substrate. The device includes a silicon carbide substrate having front and back surfaces facing each other, an isolating region formed in the substrate to ... | 06/26/2007 |
