Did You Know...
...that power steering was invented by independent inventor Francis W. Davis? As chief engineer in the 1920s of the truck division of the Pierce Arrow Motor Car Company, he saw how hard it was to steer heavy vehicles. So that he would be able to keep the profits from his future invention, Davis left his job, rented a small engineering shop in Waltham, Mass., and developed a hydraulic power steering system that led to power steering.
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| Number | Title | Issue Date |
| 7981771 | Structures and methods to enhance Cu interconnect electromigration (EM) performance The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in interconnects. A method includes forming an interconnect, forming a cap on the interconnect, and forming a pl... | 07/19/2011 |
| 7915144 | Methods for forming thermotunnel generators having closely-spaced electrodes The present disclosure relates to methods of forming solid state thermal engines that provides a closely-spaced thermal tunneling gap between a hot and cold electrode. The effective gap may be on the order of one nanometer. In one embodiment, a via is etched through... | 03/29/2011 |
| 7301239 | Wiring structure to minimize stress induced void formation A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n”... | 11/27/2007 |
| 7276435 | Die level metal density gradient for improved flip chip package reliability An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to... | 10/02/2007 |
| 7259090 | Copper damascene integration scheme for improved barrier layers A metal filled dual damascene structure with a reduced capacitance contribution and method for forming the same, the method including forming a first metal filled damascene lined with a first metal barrier layer thickness in a first dielectric insulating layer; and,... | 08/21/2007 |
| 7232771 | Method and apparatus for depositing charge and/or nanoparticles A method and apparatus for use in depositing electrical charge and/or nanoparticles is provided. A stamping process is used in which a stamp having a flexible layer such as a flexible semiconductor layer applies a charge pattern on a substrate. Other techniques incl... | 06/19/2007 |
| 7205638 | Silicon building blocks in integrated circuit packaging An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead w... | 04/17/2007 |
| 7190048 | Resistance variable memory device and method of fabrication Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least on... | 03/13/2007 |
| 7148105 | Method for forming polysilicon floating gate A floating gate memory cell comprises a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. The depositi... | 12/12/2006 |
| 7145241 | Semiconductor device having a multilayer interconnection structure and fabrication process thereof A multilayer interconnection structure includes a first interconnection layer having a copper interconnection pattern and a second interconnection layer having an aluminum interconnection layer and formed on the first interconnection layer via an intervening interla... | 12/05/2006 |
| 7083425 | Slanted vias for electrical circuits on circuit boards and other substrates Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting electronic components includes a dielectric portion having a first surface and a second surface. A first term... | 08/01/2006 |
| 7045455 | Via electromigration improvement by changing the via bottom geometric profile An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion b... | 05/16/2006 |
| 7026225 | Semiconductor component and method for precluding stress-induced void formation in the semiconductor component A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over t... | 04/11/2006 |
| 6975047 | Temperature-based cooling device controller apparatus and method A temperature-based cooling device controller is implemented in an integrated circuit such as a microprocessor. The temperature-based cooling device controller includes a register to store a threshold temperature value, a thermal sensor, and clock adjustment logic t... | 12/13/2005 |
| 6953742 | Tantalum barrier layer for copper metallization A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rath... | 10/11/2005 |
| 6933591 | Electrically-programmable integrated circuit fuses and sensing circuits Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by... | 08/23/2005 |
| 6927113 | Semiconductor component and method of manufacture A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched ... | 08/09/2005 |
| 6881594 | Method of using scatterometry for analysis of electromigration, and structures for performing same The present invention is generally directed to various methods of using scatterometry for analysis of electromigration. In one illustrative embodiment, the method comprises forming a grating structure above a semiconducting substrate, the grating structure being com... | 04/19/2005 |
| 6881261 | Method for fabricating semiconductor device A p-type InGaAlN layer, an InGaAlN active layer, and an n-type InGaAlN layer each having a composition represented by (AlxGa1-x)yIn1-yN (0≦x≦1, 0≦y≦1) are formed on a sapphire substrate. In the as-grown state, Mg i... | 04/19/2005 |
| 6867056 | System and method for current-enhanced stress-migration testing of interconnect For testing for stress-migration failure of interconnect, an interconnect test structure is formed with a first feeder line coupled to a test line by a first no-flux structure, and with a second feeder line coupled to the test line by a second no-flux structure. A r... | 03/15/2005 |
| 6844245 | Method of preparing a self-passivating Cu laser fuse A method of forming a semiconductor device, such as a self-passivating fuse, includes patterning an opening in a dielectric to form a fuse. A seed-layer of a copper-alloy is deposited in the opening and the opening is filled with pure copper. The copper is planarize... | 01/18/2005 |
| 6784000 | Method for measurement of electromigration in semiconductor integrated circuits Electromigration testing is accelerated in the batch fabrication of semiconductor integrated circuits by forming test structures during the metal deposition phase of the batch fabrication process. Test metal lines can be formed on steps etched in a silicon oxide ins... | 08/31/2004 |
| 6777314 | Method of forming electrolytic contact pads including layers of copper, nickel, and gold A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is formed in a substantially contiguous sheet across the surface of the ... | 08/17/2004 |
| 6756258 | Method of manufacturing a semiconductor device A method of fabricating silicon TFTs (thin-film transistors) is disclosed. The method comprises a crystallization step by laser irradiation effected after the completion of the device structure. First, amorphous silicon TFTs are fabricated. In each of the TFTs, the ... | 06/29/2004 |
| 6624499 | System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled ... | 09/23/2003 |
| 6593213 | Synthesis of layers, coatings or films using electrostatic fields Systems and methods are described for synthesis of films, coatings or layers using electrostatic fields. A method includes applying an electrostatic field across a first precursor layer that is coupled to a first substrate and a second precursor layer tha... | 07/15/2003 |
| 6548377 | Method for forming a line of semiconductor device A method for forming a line of a semiconductor device is provided, which improves the life span of the line and its reliability by improving resistance to electromigration (EM). The method for forming a line of a semiconductor device includes forming a fi... | 04/15/2003 |
| 6513000 | Simulation method of wiring temperature rise A heat capacity C1 is obtained by conducting two-dimensional thermal analysis simulation to the cross-section of a wiring. Next, based on one-dimensional approximate equation of θ0 =(Q0 /2) (λ.multidot.SC1)-1/... | 01/28/2003 |
| 6417053 | Fabrication method for a silicon nitride read-only memory A fabrication method for a silicon nitride read-only memory is described. A silicon nitride read-only memory and a grounding doped region are formed in the substrate. A contact is formed on the substrate. A metal protection line is also formed, wherein th... | 07/09/2002 |
| 6362079 | Semiconductor device and method of anodization for the semiconductor device A first p-type silicon layer (3) is formed as a buried layer in a p-type single crystal silicon substrate (2), and an n-type silicon layer (4) is formed on the upper side of the silicon substrate (2). A second p-type silicon layer (5) for forming an openi... | 03/26/2002 |
| 6306732 | Method and apparatus for simultaneously improving the electromigration reliability and resistance of damascene vias using a controlled diffusivity barrier An apparatus for improving electromigration reliability and resistance of a single- or dual-damascene via includes an imperfect barrier formed at the bottom of the via, and a stronger barrier formed at all other portions of the via. The imperfect barrier ... | 10/23/2001 |
| 6156626 | Electromigration bonding process and system A process and system for connecting a semiconductor chip to a substrate is provided. The process includes providing the substrate that is configured to receive the semiconductor chip that has a bonding pad. The substrate has a first side that is suited to... | 12/05/2000 |
| 6136619 | Method for measuring electromigration-induced resistance changes A method for measuring resistance changes is described to study electromigration induced failures in conductive patterns. This method can provide a basis for lifetime predictions based on low value failure criteria, i.e. small resistance changes in the co... | 10/24/2000 |
| 6136669 | Mobile charge immune process A semi conductor manufacturing process including uniform negative polarity wafer charging to remove or immobilize alkali ions such that the device becomes immune to their presence. The wafer is charged with a corona discharge at a 1MV/cm-2MV/cm bias field... | 10/24/2000 |
| 6072945 | System for automated electromigration verification An automated apparatus detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are pro... | 06/06/2000 |
| 5963729 | Method for automated electromigration verification An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propag... | 10/05/1999 |
| 5963831 | Method of making an interconnect structure employing equivalent resistance paths to improve electromigration resistance A method of fabricating an interconnect structure having improved electromigration resistance. Two conductive lines are formed over a substrate and isolated by a dielectric layer. A contact/via array including a plurality of row contact/vias and column co... | 10/05/1999 |
| 5959360 | Interconnect structure employing equivalent resistance paths to improve electromigration resistance A structure of a conductive line. The structure of a conductive line comprises a substrate with two conductive lines formed thereon. These two conductive lines are isolated by the formation of a dielectric layer. The conductive lines are electrically conn... | 09/28/1999 |
| 5714400 | Method for forming a memory device by utilizing variations in resistance value On an insulating substrate are formed first aluminum interconnections. In openings formed in a silicon dioxide film are formed unit cells each consisting of a tungsten electrode and an aluminum alloy electrode containing silicon. Over the silicon dioxide ... | 02/03/1998 |
| 5665627 | Method of irreversibly locking a portion of a semiconductor device A fuse for an integrated circuit is constituted by a shallow NP junction, covered with a metal contact, the semiconductor region being not excessively doped. For the blowing of the fuse, the junction is forward biased with a current sufficient to enable a... | 09/09/1997 |
