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| Number | Title | Issue Date |
| 8114751 | Multi-angle rotation for ion implantation of trenches in superjunction devices A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench i... | 02/14/2012 |
| 8012843 | Optimized halo or pocket cold implants An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the mi... | 09/06/2011 |
| 7888226 | Method of fabricating power semiconductor device for suppressing substrate recirculation current A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a f... | 02/15/2011 |
| 7468305 | Forming pocket and LDD regions using separate masks A method of decoupling the formation of LDD and pocket regions is provided. The method includes providing a semiconductor chip including active regions, forming gate structures in the active regions, forming N-LDD regions on the semiconductor chip using an N-LDD mas... | 12/23/2008 |
| 7439092 | Thin film splitting method A method of fabricating thin films of semiconductor materials by implanting ions in a substrate composed of at least two different elements at least one of which can form a gaseous phase on bonding with itself and/or with impurities includes the following steps: | 10/21/2008 |
| 7341929 | Method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control A method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control is provided. An ion-implanting area is first defined on a silicon substrate, and then proceeds ion-implanting. Finally, a buffer layer and a SiGe epitaxial layer... | 03/11/2008 |
| 7314805 | Method for fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of ... | 01/01/2008 |
| 7300851 | Method of fabricating a silicon-on-insulator device with a channel stop A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral par... | 11/27/2007 |
| 7276421 | Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor ... | 10/02/2007 |
| 7271443 | Semiconductor device and manufacturing method for the same A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region inclu... | 09/18/2007 |
| 7253072 | Implant optimization scheme The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405... | 08/07/2007 |
| 7253067 | Method for manufacturing a semiconductor device including a shallow trench isolation structure A method of manufacturing a semiconductor device having a semiconductor substrate that includes an active region for forming transistor elements, which includes a gate, and an element isolation region for isolating the transistor elements separately each other, whic... | 08/07/2007 |
| 7247867 | Ion implanter and method of manufacturing semiconductor device An ion implanter includes a sample stage for setting a sample having a main surface, an ion generating section configured to generate a plurality of ions, the ion generating section including a container into which an ion source gas is introduced and a filament for ... | 07/24/2007 |
| 7220649 | Method of manufacturing semiconductor device and the semiconductor device manufactured by the method The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate ins... | 05/22/2007 |
| 7195986 | Microfluidic device with controlled substrate conductivity A method to achieve controlled conductivity in microfluidic devices, and a device formed thereby. The method comprises forming a microchannel or a well in an insulating material, and ion implanting at least one region of the insulating material at or adjacent the mi... | 03/27/2007 |
| 7169674 | Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and ... | 01/30/2007 |
| 7157346 | Method of reducing charging damage to integrated circuits during semiconductor manufacturing An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semico... | 01/02/2007 |
| 7144787 | Methods to improve the SiGe heterojunction bipolar device performance Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a... | 12/05/2006 |
| 7118983 | Method of fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of ... | 10/10/2006 |
| 7112501 | Method of fabrication a silicon-on-insulator device with a channel stop A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral par... | 09/26/2006 |
| 7101746 | Method to lower work function of gate electrode through Ge implantation A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon laye... | 09/05/2006 |
| 7049225 | Method for manufacturing vias between conductive patterns utilizing etching mask patterns formed on the conductive patterns In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures a... | 05/23/2006 |
| 7049202 | Method of manufacturing semiconductor device A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into ... | 05/23/2006 |
| 7037814 | Single mask control of doping levels In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by making use of varying size and spacings to the perforations in the m... | 05/02/2006 |
| 7001856 | Method of calculating a pressure compensation recipe for a semiconductor wafer implanter A process uses pressure changes and a pressure compensation factor to estimate the rate at which neutral atoms are implanted. While implanting a first wafer using a first pressure compensation factor, the rate at which ions are implanted is determined. The first waf... | 02/21/2006 |
| 6995068 | Double-implant high performance varactor and method for manufacturing same A varactor designed to enable voltage controlled oscillator (VCO) integration in wireless systems is the base-emitter junction of a specially optimized NPN device formed with a double base implant. A first, shallow implant optimizes capacitance, leakage current, and... | 02/07/2006 |
| 6924216 | Semiconductor device having improved doping profiles and method of improving the doping profiles of a semiconductor device A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorph... | 08/02/2005 |
| 6924874 | Method of forming a liquid crystal display The present invention provides a method of forming a liquid crystal display (LCD). Active layers of N-type and P-type low temperature polysilicon thin film transistors and a bottom electrode of a storage capacitor are formed first. Then a N-type source/drain is form... | 08/02/2005 |
| 6924215 | Method of monitoring high tilt angle of medium current implant A method of monitoring and adjusting the position of a wafer with respect to an ion beam including setting the position of a wafer holder so that a wafer to be held therein is positioned at a tilt angle of 45 degrees and a twist angle of 45 degrees with respect to t... | 08/02/2005 |
| 6893931 | Reducing extrinsic base resistance in an NPN transistor A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may... | 05/17/2005 |
| 6864144 | Method of stabilizing resist material through ion implantation A resist material used to mask an underlying layer during an etch process is subjected to ion implantation to harden the resist material against damage from the etch process. In a particular embodiment, the resist material is compatible with exposure to 193 nm radia... | 03/08/2005 |
| 6852604 | Manufacturing method of semiconductor substrate A manufacturing method of a semiconductor substrate comprising the steps of: (a) forming a SiGe layer on a substrate of which the surface is made of silicon; (b) further forming a semiconductor layer on the SiGe layer; and (c) implanting ions into regions of the SiG... | 02/08/2005 |
| 6849526 | Method of improving device resistance A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region an... | 02/01/2005 |
| 6815301 | Method for fabricating bipolar transistor A method for fabricating a bipolar transistor includes: a first step of implanting, along the normal direction of the principle surface of a first-conductive-type semiconductor single crystalline substrates ions of a second-conductive-type first impurity into the se... | 11/09/2004 |
| 6812107 | Method for improved alignment tolerance in a bipolar transistor According to one exemplary embodiment, a method for fabricating a bipolar transistor, such as a heterojunction bipolar transistor (“HBT”), comprises fabricating a first inner spacer and a second inner spacer on a top surface of a base. The method further compris... | 11/02/2004 |
| 6797577 | One mask PNP (or NPN) transistor allowing high performance A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost effective manner. The method provides for fewer masking operations during bipolar junction transistor formati... | 09/28/2004 |
| 6770923 | High K dielectric film A dielectric layer comprises lanthanum, aluminum, nitrogen, and oxygen and is formed between two conductors or a conductor and substrate. In one embodiment, the dielectric layer is graded with among the lanthanum, nitrogen, or aluminum. An additional insulating laye... | 08/03/2004 |
| 6762085 | Method of forming a high performance and low cost CMOS device A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertic... | 07/13/2004 |
| 6753235 | Method of manufacturing CMOS thin film transistor A method of manufacturing a CMOS TFT including forming first and second semiconductor layers on an insulating substrate using a first mask, respectively, the substrate having first and second regions, the first semiconductor layer formed on the first region, the sec... | 06/22/2004 |
| 6740563 | Amorphizing ion implant method for forming polysilicon emitter bipolar transistor A method for fabricating a polysilicon emitter bipolar transistor employs a pair of ion implant methods. A first of the icon implant methods implants a portion of an intrinsic base region interposed between an extrinsic base region and a polysilicon emitter layer wi... | 05/25/2004 |
