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| Number | Title | Issue Date |
| 7947562 | Noise reduction in semiconductor device using counter-doping One or more embodiments describe a method of fabricating a silicon based metal oxide semiconductor device, including introducing a first dopant into a first partial completion of the device, the first dopant including a first noise reducing species; and introducing ... | 05/24/2011 |
| 7651920 | Noise reduction in semiconductor device using counter-doping One or more embodiments describe a method of fabricating a silicon based metal oxide semiconductor device, comprising: implanting a first dopant into a first partial completion of the device, the first dopant comprising a first noise reducing species; and implanting... | 01/26/2010 |
| 7439591 | Gate layer diode method and apparatus Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a ... | 10/21/2008 |
| 7422952 | Method of forming a BJT with ESD self protection A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector ... | 09/09/2008 |
| 7378324 | Selective links in silicon hetero-junction bipolar transistors using carbon doping and method of forming same Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; ... | 05/27/2008 |
| 7338877 | Multicomponent fiber including a luminescent colorant The present invention is directed to multicomponent fibers having a non-luminescent first polymeric component and a second polymeric component comprising a luminescent colorant. The second component comprises less than about 50 percent of the total cross-section of ... | 03/04/2008 |
| 7314805 | Method for fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of ... | 01/01/2008 |
| 7300851 | Method of fabricating a silicon-on-insulator device with a channel stop A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral par... | 11/27/2007 |
| 7262107 | Capacitor structure for a logic process A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used ... | 08/28/2007 |
| 7253072 | Implant optimization scheme The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405... | 08/07/2007 |
| 7253067 | Method for manufacturing a semiconductor device including a shallow trench isolation structure A method of manufacturing a semiconductor device having a semiconductor substrate that includes an active region for forming transistor elements, which includes a gate, and an element isolation region for isolating the transistor elements separately each other, whic... | 08/07/2007 |
| 7211489 | Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal The present invention enables the production of improved high-reliability, high-density semiconductor devices. The present invention provides the high-density semiconductor devices by decreasing the size of semiconductor device structures, such as gate channel lengt... | 05/01/2007 |
| 7205173 | Method of fabricating micro-electromechanical systems A MEMS incorporating a sensing element and a JFET electrically connected to the sensing element is fabricated by the steps of: forming a first layer of electrically insulating barrier material on a surface of a substrate; patterning the first layer so as to expose a... | 04/17/2007 |
| 7195986 | Microfluidic device with controlled substrate conductivity A method to achieve controlled conductivity in microfluidic devices, and a device formed thereby. The method comprises forming a microchannel or a well in an insulating material, and ion implanting at least one region of the insulating material at or adjacent the mi... | 03/27/2007 |
| 7169674 | Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and ... | 01/30/2007 |
| 7129533 | High concentration indium fluorine retrograde wells A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3. ... | 10/31/2006 |
| 7112499 | Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal A process is described to form a semiconductor device such as MOSFET or CMOS with shallow junctions in the source/drain extension regions. After forming the shallow trench isolations and the gate stack, sidewall dielectric spacers are removed. A pre-amorphizing impl... | 09/26/2006 |
| 7112501 | Method of fabrication a silicon-on-insulator device with a channel stop A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral par... | 09/26/2006 |
| 7094655 | Method of fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of ... | 08/22/2006 |
| 7094642 | Method of fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of ... | 08/22/2006 |
| 7081653 | Semiconductor memory device having mis-type transistors According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistor... | 07/25/2006 |
| 7074687 | Method for forming an ESD protection device An ESD protection device (20) comprises an N-type epitaxial collector (21), a first, lightly doped, deep base region (221) and second, highly doped, shallow base region (222) that extends a predetermined lateral dimension. The device resp... | 07/11/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7064040 | Method of fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of ... | 06/20/2006 |
| 7049202 | Method of manufacturing semiconductor device A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into ... | 05/23/2006 |
| 6995821 | Methods of reducing unbalanced DC voltage between two electrodes of reflective liquid crystal display by thin film passivation A structure (and method) for a reflective-type liquid crystal display includes a first-type electrode, a second-type electrode positioned opposite the first-type electrode and being of an opposite type than the first-type electrode and a liquid crystal material betw... | 02/07/2006 |
| 6933573 | Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation la... | 08/23/2005 |
| 6762085 | Method of forming a high performance and low cost CMOS device A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertic... | 07/13/2004 |
| 6713351 | Double diffused field effect transistor having reduced on-resistance A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of t... | 03/30/2004 |
| 6673703 | Method of fabricating an integrated circuit A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method anne... | 01/06/2004 |
| 6660608 | Method for manufacturing CMOS device having low gate resistivity using aluminum implant A CMOS device (10) having p-channel and n-channel transistors with aluminum implanted gates (20). When making the device (10), aluminum is non-selectively implanted to form a source and drain for the n-channel transistor and to reduce the resistivity of t... | 12/09/2003 |
| 6645820 | Polycrystalline silicon diode string for ESD protection of different power supply connections An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit... | 11/11/2003 |
| 6642122 | Dual laser anneal for graded halo profile Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphiz... | 11/04/2003 |
| 6611044 | Lateral bipolar transistor and method of making same A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit... | 08/26/2003 |
| 6534373 | MOS transistor with reduced floating body effect A method of fabricating an integrated circuit utilizes asymmetric source/drain junctions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS). The drain extension is deeper than the source ex... | 03/18/2003 |
| 6472287 | Manufacturing method of semiconductor with a cleansing agent The present invention aims to suppress certainly the single-crystallizing in polycrystalline silicon that is to compose an emitter electrode, as well as to prevent the interface oxide film from remaining, when a heat treatment is conducted to diffuse dopa... | 10/29/2002 |
| 6461928 | Methodology for high-performance, high reliability input/output devices and analog-compatible input/output and core devices using core device implants A method for fabricating an integrated circuit having analog and digital core devices. Using a first masking layer (118), a p-type type dopant is implanted to form drain extension regions (126, 122, 124) in the pMOS digital core region (102), pMOS I/O reg... | 10/08/2002 |
| 6423598 | Semiconductor device, a method of manufacturing the same, and a semiconductor device protective circuit A Schottky diode which provides a structure having no P-N junction while improving voltage resistance against a reverse bias when employed in combination with an insulated gate semiconductor device in particular. In order to attain the aforementioned obje... | 07/23/2002 |
| 6352901 | Method of fabricating a bipolar junction transistor using multiple selectively implanted collector regions A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via mult... | 03/05/2002 |
| 6329260 | Analog-to-digital converter and method of fabrication An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are fo... | 12/11/2001 |
