Bizarre Patents
A vest or belt is integrally formed with tubular, pet receiving passageways which extend around the wearer's body and terminate in pocket-like chambers for feeding and retrieval.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8030167 | Varied impurity profile region formation for varying breakdown voltage of devices Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first op... | 10/04/2011 |
| 7364959 | Method for manufacturing a MOS transistor A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of i... | 04/29/2008 |
| 7301221 | Controlling diffusion in doped semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements inc... | 11/27/2007 |
| 7247924 | Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysili... | 07/24/2007 |
| 7169674 | Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and ... | 01/30/2007 |
| 7067883 | Lateral high-voltage junction device A lateral high-voltage junction device for over-voltage protection of an MOS circuit includes a substrate having a first junction region separated from a second junction region by a substrate region. An MOS gate electrode overlies the substrate region and is separat... | 06/27/2006 |
| 7064042 | Self aligned compact bipolar junction transistor layout, and method of making same The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A... | 06/20/2006 |
| 6806160 | Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the current conduction path of the lateral SCR device is removed and inst... | 10/19/2004 |
| 6716712 | Process for producing two differently doped adjacent regions in an integrated semiconductor During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for producing two adjacent regions of a predetermined area in an integrated semiconductor, whereby a first regi... | 04/06/2004 |
| 6680497 | Interstitial diffusion barrier A heterojunction bipolar transistor is doped in the sub-collector layer (20) with phosphorus (24). The presence of the phosphorus causes any interstitial gallium (22) to be bonded (26) to the phosphorus (24) and move to a lattice site. The result is that ... | 01/20/2004 |
| 6455380 | Semiconductor device and method for fabricating the same A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region in... | 09/24/2002 |
| 6440794 | Method for forming an array of DRAM cells by employing a self-aligned adjacent node isolation technique In a method for forming an array of dynamic random access memory (DRAM) cells, each DRAM cell having one or more field effect transistors (FETs) and a deep trench capacitor, first, a substrate is prepared. Line type active areas (AAs) are patterned on the... | 08/27/2002 |
| 6368886 | Method of recovering encapsulated die A method of decapsulating a packaged die includes removing packaging material from the bottom section of a die-containing package to expose a die pan, removing the die pan, removing material between the die pan and the bottom surface of the die, using the... | 04/09/2002 |
| 6352901 | Method of fabricating a bipolar junction transistor using multiple selectively implanted collector regions A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via mult... | 03/05/2002 |
| 6225179 | Semiconductor integrated bi-MOS circuit having isolating regions different in thickness between bipolar area and MOS area and process of fabrication thereof A bi-MOS circuit is fabricated on first active regions assigned to the bipolar transistor and on second active regions assigned to the field effect transistors, and the field effect transistors are fabricated after said bipolar transistor, because a high-... | 05/01/2001 |
| 5994196 | Methods of forming bipolar junction transistors using simultaneous base and emitter diffusion techniques Methods of forming bipolar junction transistors include the steps of forming a semiconductor substrate having a highly doped buried collector region therein and an intrinsic collector region extending from the buried collector region to a face of the semi... | 11/30/1999 |
| 5985728 | Silicon on insulator process with recovery of a device layer from an etch stop layer A silicon on insulator (SOI) process is disclosed which includes the steps of forming an etch stop layer in a starting wafer, forming an insulating layer on the etch stop layer, bonding this wafer to a handle wafer, thinning the start wafer down to the et... | 11/16/1999 |
| 5972768 | Method of manufacturing semiconductor device having low contact resistance In a method of manufacturing a semiconductor device, an insulating film is formed on a surface of a p-type semiconductor region, and then removed from a selected portion of the p-type semiconductor region. An n-type region having a high concentration of a... | 10/26/1999 |
| 5940711 | Method for making high-frequency bipolar transistor A process for forming a structure of a high-frequency bipolar transistor on a layer of a semiconductor material with conductivity of a first type. The process includes forming a first shallow base region by implantation along a selected direction of impla... | 08/17/1999 |
| 5893743 | Process of fabricating semiconductor device A process for forming a first bipolar transistor having a single polysilicon structure and a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor on the same substr... | 04/13/1999 |
| 5840603 | Method for fabrication BiCMOS integrated circuit A first photoresist layer has opening portions in a region where an n-channel MOS transistor should be formed and in a region where a collector leading region should be formed. Then, phosphorous is implanted with taking the first photoresist layer as a ma... | 11/24/1998 |
| 5773349 | Method for making ultrahigh speed bipolar transistor An ultrahigh speed bipolar transistor has a base region which is formed from a P+ base polysilicon sidewall using a self-alignment method, and a base junction window which is formed in order to minimize the collector-base junction capacity. In ... | 06/30/1998 |
| 5716887 | Method of manufacturing BiCMOS device A semiconductor device and a method for manufacturing such a device are presented. The type of semiconductor device is one which merges one type of transistor (e.g., bipolar junction transistors) with another type (e.g., CMOS transistors). Specifically, t... | 02/10/1998 |
| 5670394 | Method of making bipolar transistor having amorphous silicon contact as emitter diffusion source The present invention teaches a method for fabricating a bipolar junction transistor ("BJT") from a semiconductor substrate having a base region, wherein the BJT comprises an increased Early voltage. The method initially comprises the step of forming a pa... | 09/23/1997 |
| 5654211 | Method for manufacturing ultra-high speed bipolar transistor A method of producing the bipolar transistor includes forming an aperture through a triple layer over an active region of an epitaxial layer, then forming a shallow polysilicon film at the bottom of the aperture. An intrinsic base region is formed by segr... | 08/05/1997 |
| 5453389 | Defect-free bipolar process A method for manufacturing bipolar semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having ... | 09/26/1995 |
| 5340752 | Method for forming a bipolar transistor using doped SOG A method for forming a bipolar transistor which employs a single drive-in step to form an emitter and a base. A layer of SOG containing a plurality of dopants is spun onto a collector, typically silicon. The dopants are driven into the collector to form t... | 08/23/1994 |
| 5185276 | Method for improving low temperature current gain of bipolar transistors A method for improving the low temperature current gain of silicon bipolar transistors by implanting a first and a second impurity of the same conductivity type into the base region to provide a high doping level base that increases bandgap narrowing with... | 02/09/1993 |
| 5137840 | Vertical bipolar transistor with recessed epitaxially grown intrinsic base region A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the... | 08/11/1992 |
| 5126278 | Method of manufacturing bipolar transistor by implanting intrinsic impurities A method of manufacturing a bipolar transistor, and more particularly to a method of manufacturing a bipolar transistor with reduced base width WB by implanting intrinsic impurities such as Ge and Sn in the base region.... | 06/30/1992 |
| 4877748 | Bipolar process for forming shallow NPN emitters A method for forming a BICMOS device having MOS devices and bipolar devices formed during the same process includes the steps of first forming bipolar and MOS regions and then patterning gate electrodes in the MOS regions to define source/drain regions on... | 10/31/1989 |
| 4857476 | Bipolar transistor process using sidewall spacer for aligning base insert An improved method for fabricating a bipolar transistor reduces base current resistance which heretofore has limited the switching frequency and current handling ability of bipolar transistors. The transistor base and emitter are formed as a diffusion thr... | 08/15/1989 |
| 4778772 | Method of manufacturing a bipolar transistor A method of manufacturing a semiconductor device by forming an N type collector layer in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains... | 10/18/1988 |
| 4774204 | Method for forming self-aligned emitters and bases and source/drains in an integrated circuit A method for forming a BICMOS device having MOS devices and bipolar devices formed during the same process includes the step of first forming bipolar MOS regions and then forming gate electrodes in the MOS regions and poly emitters in the bipolar regions.... | 09/27/1988 |
| 4728618 | Method of making a self-aligned bipolar using differential oxidation and diffusion A method for manufacturing semiconductor device with improved frequency characteristics is provided. The base resistance and the base-to-collector capacitance are reduced by minimizing a base area and a space between an emitter and the base. The minimizat... | 03/01/1988 |
| 4722908 | Fabrication of a bipolar transistor with a polysilicon ribbon In the fabrication of bipolar transistors by the single poly process, polysilicon sidewalls are formed along portions of a polysilicon layer that functions as a device contact. The sidewalls serve both as dopant sources which determine the width of underl... | 02/02/1988 |
| 4586968 | Process of manufacturing a high frequency bipolar transistor utilizing doped silicide with self-aligned masking Apart from the base fingers (10), this transistor includes a titanium silicide coating, from which the base diffusions have been formed, and a silicon nitride coating (4). The edges of sandwiches made up of bands (3) and (4) are bordered by a silica bank ... | 05/06/1986 |
| 4569123 | Method of manufacturing a semiconductor device utilizing simultaneous diffusion from an ion implanted polysilicon layer A method for manufacturing semiconductor devices is presented. The method comprises the steps of opening two windows on an insulating layer covering a semiconductor substrate, and forming a polysilicon layer over the entire surface of the insulating layer... | 02/11/1986 |
| 4559696 | Ion implantation to increase emitter energy gap in bipolar transistors The suppression of the reverse injection of the carriers in a bipolar transistor, without adversely effecting forward injection, is carried out by modifying the energy gap characteristics of the transistor so that a greater barrier to reverse injection is... | 12/24/1985 |
| 4456488 | Method of fabricating an integrated planar transistor A method is disclosed for fabricating a monolithic integrated planar transistor whose emitter region (1) is diffused into the base region (3) on one surface side of a semiconductor wafer (2), which base region is diffused into the collector region (4). To... | 06/26/1984 |
