Class 438/370 - Forming buried region (e.g., implanting through insulating layer, etc.)

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process wherein the dopant is implanted or diffused through
No. of patents: 189
Last issue date: 02/23/2010

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Number	Title	Issue Date
7666750	Bipolar device having improved capacitance The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak do...	02/23/2010
7563685	Bipolar-transistor and method for the production of a bipolar-transistor The invention relates to NPN and PNP bipolar transistors and to a method for the production thereof, said transistors being characterised by a particularly high collector-emitter and collector-base blocking voltage. The blocking voltage is increased by a particular ...	07/21/2009
7485539	Strained semiconductor-on-insulator (sSOI) by a simox method A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion...	02/03/2009
7456071	Method for forming a strongly-conductive buried layer in a semiconductor substrate An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material. ...	11/25/2008
7422952	Method of forming a BJT with ESD self protection A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector ...	09/09/2008
7368361	Bipolar junction transistors and method of manufacturing the same A substrate has a collector region of a first conductivity type, and a base layer of a single crystalline structure and including impurities of a second conductivity type is located over the collector region. An emitter region is defined at least in part by impuriti...	05/06/2008
7351637	Semiconductor transistors having reduced channel widths and methods of fabricating same A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The method further includes disposing a screening layer and implanting a...	04/01/2008
7314792	Method for fabricating transistor of semiconductor device A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to fo...	01/01/2008
7304354	Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol...	12/04/2007
7271447	Semiconductor device A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and that has an etching selection ratio smaller than that of the first semic...	09/18/2007
7271070	Method for producing transistors The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is de...	09/18/2007
7268376	Bipolar transistor for increasing signal transfer efficiency and method of manufacturing the same A bipolar transistor having a base semiconductor layer structure to minimize base parasitic resistance and a method of manufacturing the bipolar transistor are provided. In the provided bipolar transistor, a collector region of a second conductivity type, which is d...	09/11/2007
7253072	Implant optimization scheme The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405...	08/07/2007
7205202	Semiconductor device and method for regional stress control Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be form...	04/17/2007
7154724	Output buffer ESD protection using parasitic SCR protection circuit for CMOS VLSI integrated circuits An input and output (I/O) circuit with an improved ESD protection is disclosed. The circuit has an output buffer having an NMOS transistor coupled to a PMOS transistor, an ESD protection circuit having a parasitic silicon controlled rectifier (SCR) integrated therei...	12/26/2006
7135417	Method of forming a semiconductor device In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxida...	11/14/2006
7118981	Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component ...	10/10/2006
7091100	Polysilicon bipolar transistor and method of manufacturing it In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor substrate, a poly-crystal base terminal layer is produced on the etch stop layer and an emitter window is etched ...	08/15/2006
7087979	Bipolar transistor with an ultra small self-aligned polysilicon emitter The intrinsic base region of a bipolar transistor is formed to avoid a chemical interaction between the chemicals used in a chemical mechanical polishing step and the materials used to form the base region. The method includes the step of forming a trench in a layer...	08/08/2006
7078325	Process for producing a doped semiconductor substrate A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and acc...	07/18/2006
7067383	Method of making bipolar transistors and resulting product A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a ...	06/27/2006
7067425	Method of manufacturing flash memory device A method of manufacturing a flash memory device includes the steps of forming a nitride film on an entire surface of a trench by means of an annealing process to prevent implanted ions for adjusting a threshold voltage from diffusing to a device isolation region, an...	06/27/2006
7060583	Method for manufacturing a bipolar transistor having a polysilicon emitter In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an ins...	06/13/2006
7052966	Deep N wells in triple well structures and method for fabricating same A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the ...	05/30/2006
7026666	Self-aligned NPN transistor with raised extrinsic base A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase i...	04/11/2006
7008836	Method to provide a triple well in an epitaxially based CMOS or BiCMOS process A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition. ...	03/07/2006
6905935	Method for fabricating a vertical bipolar junction transistor A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third do...	06/14/2005
6872645	Methods of positioning and/or orienting nanostructures Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and p...	03/29/2005
6838348	Integrated process for high voltage and high performance silicon-on-insulator bipolar devices High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (2...	01/04/2005
6818490	Method of fabricating complementary high-voltage field-effect transistors A method of fabricating complementary high-voltage field-effect transistors in a substrate of a first conductivity type includes forming first and second well regions of a second conductivity type in the substrate. A first drain region of the second conductivity typ...	11/16/2004
6797596	Sacrificial deposition layer as screening material for implants into a wafer during the manufacture of a semiconductor device A method used during the formation of a semiconductor device reduces ion channeling during implantation of the wafer. The method comprises providing a semiconductor wafer and an unetched transistor gate stack assembly over the wafer. The unetched transistor gate sta...	09/28/2004
6777302	Nitride pedestal for raised extrinsic base HBT process A method of fabricating a high-performance, raised extrinsic base HBT having a narrow emitter width is provided. In accordance with the method, a patterned nitride pedestal region and inner spacers are employed to reduce the width of an emitter opening. The reduced ...	08/17/2004
6709941	Method for manufacturing semiconductor device employing solid phase diffusion In a method for manufacturing a semiconductor device, an N type single-crystal silicon substrate having a first silicon oxide film and a P type poly-crystal silicon layer is provided. A silicon nitride film is formed on the P type poly-crystal silicon layer. A side ...	03/23/2004
6709913	Method for adjusting ultra-thin SOI MOS transistor threshold voltages A method of adjusting the threshold voltage in an ultra-thin SOI MOS transistor includes preparing a SOI substrate; thinning the SOI top silicon film to a thickness of between about 10 nm and 50 nm; forming an absorption layer on the top silicon film; and implanting...	03/23/2004
6607960	Bipolar transistor manufacturing method A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a seco...	08/19/2003
6579773	Transistor device and fabrication method thereof In the fabrication of a transistor device, particularly a low-voltage high-frequency transistor for use in mobile telecommunications, a method for improving the transistor performance and the high-frequency characteristics of the device is described. The ...	06/17/2003
6538294	Trenched semiconductor device with high breakdown voltage An arrangement in a semiconductor component includes a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and ...	03/25/2003
6518139	Power semiconductor device structure with vertical PNP transistor A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and...	02/11/2003
6506656	Stepped collector implant and method for fabrication The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a ste...	01/14/2003
6455391	Method of forming structures with buried regions in a semiconductor device A monocrystalline silicon substrate is subjected to the following operations: implantation of doping impurities in a high concentration to form a planar region of a first type; selective anisotropic etching in order to hollow out trenches to a depth great...	09/24/2002

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Class 438/370 - Forming buried region (e.g., implanting through insulating layer, etc.)