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| Number | Title | Issue Date |
| 8153496 | Self-aligned process and method for fabrication of high efficiency solar cells An improved method of doping a substrate is disclosed. The method is particularly beneficial to the creation of interdigitated back contact (IBC) solar cells. A patterned implant is performed to introduce a first dopant to a portion of the solar cell. After this imp... | 04/10/2012 |
| 8153495 | Semiconductor device and LTPS-TFT within and method of making the same A thin film transistor (TFT) formed on a substrate includes a polycrystalline film, a gate insulator, a hydrogen-supplying film and a gate electrode. The polycrystalline film is formed on the substrate. Two sides of the polycrystalline film serve as the source and t... | 04/10/2012 |
| 7939418 | Partial implantation method for semiconductor manufacturing Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a ... | 05/10/2011 |
| 7759211 | Method of fabricating semiconductor device There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substr... | 07/20/2010 |
| 7642169 | Method of making a bipolar junction transistor Embodiments relate to a bipolar junction transistor and a method for manufacturing the same. An oxide pattern may be formed on a P type semiconductor substrate. A low-density N type collector area may be formed in the semiconductor substrate. First spacers may be fo... | 01/05/2010 |
| 7572708 | Utilization of doped glass on the sidewall of the emitter window in a bipolar transistor structure A bipolar transistor device architecture and method of manufacture uses doped glass on the sidewall of the emitter window opening to reduce the emitter-base overlap capacitance while at the same time improving the polysilicon plugging effect. The doped glass sidewal... | 08/11/2009 |
| 7550358 | MEMS device including a laterally movable portion with piezo-resistive sensing elements and electrostatic actuating elements on trench side walls, and methods for producing the same A method to create piezoresistive sensing elements and electrostatic actuator elements on trench sidewalls is disclosed. P-type doped regions are formed in the upper surface of an n-type substrate. A trench is formed in the substrate (e.g. by DRIE process) intersect... | 06/23/2009 |
| 7442616 | Method of manufacturing a bipolar transistor and bipolar transistor thereof A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154... | 10/28/2008 |
| 7439591 | Gate layer diode method and apparatus Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a ... | 10/21/2008 |
| 7435659 | Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implan... | 10/14/2008 |
| 7429525 | Fabrication process of a semiconductor device A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing... | 09/30/2008 |
| 7413996 | High k gate insulator removal A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed por... | 08/19/2008 |
| 7364978 | Method of fabricating semiconductor device There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substr... | 04/29/2008 |
| 7361567 | Non-volatile nanocrystal memory and method therefor A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentra... | 04/22/2008 |
| 7361548 | Methods of forming a capacitor using an atomic layer deposition process Methods for forming a capacitor using an atomic layer deposition process include providing a reactant including an aluminum precursor onto a substrate to chemisorb a portion of the reactant to a surface of the substrate. The substrate has an underlying structure inc... | 04/22/2008 |
| 7358171 | Method to chemically remove metal impurities from polycide gate sidewalls An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also... | 04/15/2008 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7338875 | Method of fabricating a semiconductor device having a toroidal-like junction Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is ... | 03/04/2008 |
| 7338876 | Method for manufacturing a semiconductor device A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor subs... | 03/04/2008 |
| 7338894 | Semiconductor device having nitridated oxide layer and method therefor A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15 | 03/04/2008 |
| 7314794 | Low-cost high-performance planar back-gate CMOS A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-ga... | 01/01/2008 |
| 7314804 | Plasma implantation of impurities in junction region recesses A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in j... | 01/01/2008 |
| 7309656 | Method for forming step channel of semiconductor device A method for forming a step channel of a semiconductor device is disclosed. The method for forming a step channel of a semiconductor device comprises forming a hard mask layer pattern defining a step channel region on a semiconductor substrate, forming a spacer on a... | 12/18/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7253072 | Implant optimization scheme The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405... | 08/07/2007 |
| 7253071 | Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer pr... | 08/07/2007 |
| 7239007 | Bipolar transistor with divided base and emitter regions A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electricall... | 07/03/2007 |
| 7235861 | NPN transistor having reduced extrinsic base resistance and improved manufacturability A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may... | 06/26/2007 |
| 7226835 | Versatile system for optimizing current gain in bipolar transistor structures Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406 | 06/05/2007 |
| 7217628 | High performance integrated vertical transistors and method of making the same A complementary bipolar transistor is fabricated using an available portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collec... | 05/15/2007 |
| 7214616 | Homojunction semiconductor devices with low barrier tunnel oxide contacts A homojunction bipolar transistor with performance characteristics similar to more costly heterojunction or retrograde base transistors. The high emitter resistivity found in prior homojunction devices is circumvented using a low work function material layer in form... | 05/08/2007 |
| 7211863 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 05/01/2007 |
| 7202536 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 04/10/2007 |
| 7195986 | Microfluidic device with controlled substrate conductivity A method to achieve controlled conductivity in microfluidic devices, and a device formed thereby. The method comprises forming a microchannel or a well in an insulating material, and ion implanting at least one region of the insulating material at or adjacent the mi... | 03/27/2007 |
| 7190047 | Transistors and methods for making the same Apparatus comprising: a first compound semiconductor composition layer doped to have a first charge carrier polarity; a second compound semiconductor composition layer doped to have a second charge carrier polarity and located on the first layer; a third compound se... | 03/13/2007 |
| 7169677 | Method for producing a spacer structure A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering depo... | 01/30/2007 |
| 7160806 | Thermal inkjet printhead processing with silicon etching A method of etching the trench portions of a thermal inkjet printhead using a robust mask that precisely defines the area of the substrate surface to be etched and that protects the adjacent drop generator components from damaging exposure to the silicon etchant. Th... | 01/09/2007 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
