Did You Know...
...that the x-ray was discovered purely by accident? When German physicist Wilhelm Konrad von Roentgen was experimenting with cathode rays in 1895, he put an activated Crookes tube in a book and went out to lunch. When he returned, he discovered that a key that had also been placed in the book showed up as an image on the developed film!
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| Number | Title | Issue Date |
| 7538004 | Method of fabrication for SiGe heterojunction bipolar transistor (HBT) A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base a... | 05/26/2009 |
| 7534691 | Isolation structures for preventing photons and carriers from reaching active areas and methods of formation Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electro... | 05/19/2009 |
| 7410878 | Polysilicon film having smooth surface and method of forming the same A method of forming a polysilicon film having smooth surface using a lateral growth and a step-and-repeat laser process. Amorphous silicon formed in a first irradiation region of a substrate is crystallized to form a first polysilicon region by a first laser shot. T... | 08/12/2008 |
| 7338875 | Method of fabricating a semiconductor device having a toroidal-like junction Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is ... | 03/04/2008 |
| 7232732 | Semiconductor device with a toroidal-like junction Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is ... | 06/19/2007 |
| 7217609 | Semiconductor fabrication process, lateral PNP transistor, and integrated circuit A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n+-type region; forming field isolation areas around ... | 05/15/2007 |
| 7211877 | Chip scale surface mount package for semiconductor device and process of fabricating the same A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not ext... | 05/01/2007 |
| 7169674 | Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and ... | 01/30/2007 |
| 7112491 | Methods of forming field effect transistors including floating gate field effect transistors The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes f... | 09/26/2006 |
| 7112500 | Thin film transistor, liquid crystal display and manufacturing method thereof The present invention provides a thin film transistor comprising a drain electrode and a source electrode separated by a channel region formed over a contact portion with an amorphous silicon layer and wherein an impurity from the channel region is removed and a rem... | 09/26/2006 |
| 7105415 | Method for the production of a bipolar transistor The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein and is bare towards the top. A monocrystalline base area is provided... | 09/12/2006 |
| 7074690 | Selective gap-fill process Methods for selectively depositing a solid material on a substrate having gaps of dimension on the order of about 100 nm or less are disclosed. The methods involve exposing the substrate to a precursor of a solid material, such that the precursor forms liquid region... | 07/11/2006 |
| 7049231 | Methods of forming capacitors In but one aspect of the invention, a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A ... | 05/23/2006 |
| 7026666 | Self-aligned NPN transistor with raised extrinsic base A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase i... | 04/11/2006 |
| 7005359 | Bipolar junction transistor with improved extrinsic base region and method of fabrication A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter... | 02/28/2006 |
| 6881987 | pMOS device having ultra shallow super-steep-retrograde epi-channel with dual channel doping and method for fabricating the same The present invention provides a p-channel metal-oxide-semiconductor (pMOS) device having an ultra shallow epi-channel satisfying a high doping concentration required for a device of which gate length is about 30 nm even without using a HALO doping layer and a metho... | 04/19/2005 |
| 6872638 | Method of manufacturing a semiconductor device A method of performing irradiation of laser light is given as a method of crystallizing a semiconductor film. However, if laser light is irradiated to a semiconductor film, the semiconductor film is instantaneously melted and expands locally. The temperature gradien... | 03/29/2005 |
| 6869854 | Diffused extrinsic base and method for fabrication The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced ... | 03/22/2005 |
| 6800541 | Pulse laser irradiation method for forming a semiconductor thin film A method of irradiation of plural pulse laser beams onto one position of a non-single crystal semiconductor, wherein the pulse laser beams are not higher in energy density than an energy density threshold value necessary for causing a micro-crystallization of the no... | 10/05/2004 |
| 6790737 | Method for fabricating thin metal layers from the liquid phase A method for producing metal layers on surfaces of semiconductor substrates includes the step of providing a semiconductor substrate having a surface. In this case, a precursor compound of a metal to be deposited is condensed out on the semiconductor surface and sub... | 09/14/2004 |
| 6740560 | Bipolar transistor and method for producing same The aim of the invention is to provide for a bipolar transistor and a method for producing the same. Said bipolar transistor should have minimal base-emitter capacities and very good high frequency characteristics. The static characteristics, especially the base cur... | 05/25/2004 |
| 6656812 | Vertical bipolar transistor having little low-frequency noise and high current gain, and corresponding fabrication process A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collect... | 12/02/2003 |
| 6642121 | Control of amount and uniformity of oxidation at the interface of an emitter region of a monocrystalline silicon wafer and a polysilicon layer formed by chemical vapor deposition A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the react... | 11/04/2003 |
| 6617220 | Method for fabricating an epitaxial base bipolar transistor with raised extrinsic base An epitaxial base bipolar transistor including an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on a portion of the single crystal layer; a raised extrinsic base on a surface of the semiconductor substrate; an insul... | 09/09/2003 |
| 6506655 | Bipolar transistor manufacturing method A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an... | 01/14/2003 |
| 6362034 | Method of forming MOSFET gate electrodes having reduced depletion region growth sensitivity to applied electric field A method of fabricating a FET having a gate electrode with reduced susceptibility to the carrier depletion effect, includes increasing the amount of n-type dopant in the gate electrode of an n-channel FET. In one embodiment of the present invention, an in... | 03/26/2002 |
| 6319786 | Self-aligned bipolar transistor manufacturing method The manufacturing of a bipolar transistor, including the steps of depositing a P-type polysilicon layer and an insulating layer on an N-type substrate; defining in said layers a base-emitter opening; performing a P-type doping and annealing to form a heav... | 11/20/2001 |
| 6248650 | Self-aligned BJT emitter contact A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region. and a base link-up region within the collector region between the intrinsic base region and the e... | 06/19/2001 |
| 6194280 | Method for forming a self-aligned BJT emitter contact A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, and a base link-up region within the collector region between the intrinsic base region and the e... | 02/27/2001 |
| 6180442 | Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer... | 01/30/2001 |
| 6156594 | Fabrication of bipolar/CMOS integrated circuits and of a capacitor The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, ope... | 12/05/2000 |
| 6130136 | Bipolar transistor with L-shaped base-emitter spacer A method for fabricating a spacer in a transistor. The method comprises the steps of forming a stepped feature 384, 386 at a surface of a semiconductor body 340, the stepped feature having a lateral face substantially parallel to the surface and an angled... | 10/10/2000 |
| 6114208 | Method for fabricating complementary MOS transistor A method for fabricating complementary metal-oxide-semiconductor (CMOS) devices and circuits resulting therefrom are provided. The method includes forming the source and drain regions of the CMOS device by out-diffusion of ions injected into a conductive ... | 09/05/2000 |
| 6080601 | Method for forming a bipolar-based active pixel sensor cell with metal contact and increased capacitive coupling to the base region The dynamic range is increased and the noise level is reduced in a bipolar-based active pixel sensor cell with a capacitively coupled base region by forming the capacitor over a portion of the base region and the field oxide region of the cell. In additio... | 06/27/2000 |
| 6077752 | Method in the manufacturing of a semiconductor device A method of manufacturing a bipolar transistor having a self-registered base-emitter structure is provided. The method involves the steps of: depositing a layer of amorphous silicon on a substrate of crystalline silicon having an upper region of a first c... | 06/20/2000 |
| 6004855 | Process for producing a high performance bipolar structure A process for producing a small shallow-depth high-performance bipolar structure having low parasitic capacitance is disclosed wherein an active base region of a P-type material is first defined in a substrate, a portion of which is of N-type material in ... | 12/21/1999 |
| 5994196 | Methods of forming bipolar junction transistors using simultaneous base and emitter diffusion techniques Methods of forming bipolar junction transistors include the steps of forming a semiconductor substrate having a highly doped buried collector region therein and an intrinsic collector region extending from the buried collector region to a face of the semi... | 11/30/1999 |
| 5985728 | Silicon on insulator process with recovery of a device layer from an etch stop layer A silicon on insulator (SOI) process is disclosed which includes the steps of forming an etch stop layer in a starting wafer, forming an insulating layer on the etch stop layer, bonding this wafer to a handle wafer, thinning the start wafer down to the et... | 11/16/1999 |
| 5940711 | Method for making high-frequency bipolar transistor A process for forming a structure of a high-frequency bipolar transistor on a layer of a semiconductor material with conductivity of a first type. The process includes forming a first shallow base region by implantation along a selected direction of impla... | 08/17/1999 |
| 5882976 | Method of fabricating a self-aligned double polysilicon NPN transistor with poly etch stop A method of forming a double polysilicon NPN transistor using a self-aligned process flow. The method includes use of a sacrificial oxide layer deposited over an epitaxial silicon layer prior to deposition and doping of the polysilicon layer from which th... | 03/16/1999 |