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| Number | Title | Issue Date |
| 7226835 | Versatile system for optimizing current gain in bipolar transistor structures Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406 | 06/05/2007 |
| 7202514 | Self aligned compact bipolar junction transistor layout and method of making same The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A... | 04/10/2007 |
| 7166524 | Method for ion implanting insulator material to reduce dielectric constant An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielec... | 01/23/2007 |
| 7041564 | Method for fabricating a self-aligned bipolar transistor According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transist... | 05/09/2006 |
| 7038298 | High fand fbipolar transistor and method of making same A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (112) that extends beyond the lower... | 05/02/2006 |
| 6972471 | Deep trench isolation structure of a high-voltage device and method for forming thereof A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial l... | 12/06/2005 |
| 6940149 | Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap inc... | 09/06/2005 |
| 6905935 | Method for fabricating a vertical bipolar junction transistor A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third do... | 06/14/2005 |
| 6900519 | Diffused extrinsic base and method for fabrication The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced ... | 05/31/2005 |
| 6869854 | Diffused extrinsic base and method for fabrication The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced ... | 03/22/2005 |
| 6846716 | Integrated circuit device and method therefor A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the ... | 01/25/2005 |
| 6808999 | Method of making a bipolar transistor having a reduced base transit time A bipolar transistor has a high performance and high reliability, which are obtained by enhancing a withstanding voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, an opening dispose... | 10/26/2004 |
| 6764918 | Structure and method of making a high performance semiconductor device having a narrow doping profile A structure and method of making an NPN heterojunction bipolar transistor (100) includes a semiconductor substrate (11) with a first region (82) containing a dopant (86) for forming a base region of the transistor. A second region (84 | 07/20/2004 |
| 6713361 | Method of manufacturing a bipolar junction transistor including undercutting regions adjacent to the emitter region to enlarge the emitter region According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilico... | 03/30/2004 |
| 6661055 | Transistor in semiconductor devices The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and forme... | 12/09/2003 |
| 6656822 | Method for reduced capacitance interconnect system using gaseous implants into the ILD A method of decreasing the dielectric constant of a dielectric layer. First, a dielectric layer is formed on a first conductive layer. A substance is then implanted into the dielectric layer.... | 12/02/2003 |
| 6617220 | Method for fabricating an epitaxial base bipolar transistor with raised extrinsic base An epitaxial base bipolar transistor including an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on a portion of the single crystal layer; a raised extrinsic base on a surface of the semiconductor substrate; an insul... | 09/09/2003 |
| 6500721 | Bipolar thin-film transistors and method for forming A bipolar junction transistor includes a substrate, a first layer, a second layer, and a third layer. The first layer comprises non-single-crystalline semiconductor material having a first conductivity type deposited on the substrate. The second layer com... | 12/31/2002 |
| 6387768 | Method of manufacturing a semiconductor component and semiconductor component thereof A method of manufacturing a semiconductor component includes providing a substrate (110), an electrically insulative layer (710 or 810) over the substrate, and an electrically conductive layer (820) over the electrically insulative layer. A hole (1510) is... | 05/14/2002 |
| 6368886 | Method of recovering encapsulated die A method of decapsulating a packaged die includes removing packaging material from the bottom section of a die-containing package to expose a die pan, removing the die pan, removing material between the die pan and the bottom surface of the die, using the... | 04/09/2002 |
| 6180442 | Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer... | 01/30/2001 |
| 6156594 | Fabrication of bipolar/CMOS integrated circuits and of a capacitor The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, ope... | 12/05/2000 |
| 6117719 | Oxide spacers as solid sources for gallium dopant introduction Impurities are formed in the active region of a semiconductor substrate by diffusion from a gate electrode sidewall spacer. A gate electrode is formed on a semiconductor substrate with a gate dielectric layer therebetween. Sidewall spacers are formed on t... | 09/12/2000 |
| 6077736 | Method of fabricating a semiconductor device A method of fabricating a semiconductor device includes the steps of preparing a semiconductor substrate having a first region and a second region, forming a first gate electrode and a second gate electrode over the semiconductor substrate at the first an... | 06/20/2000 |
| 5994196 | Methods of forming bipolar junction transistors using simultaneous base and emitter diffusion techniques Methods of forming bipolar junction transistors include the steps of forming a semiconductor substrate having a highly doped buried collector region therein and an intrinsic collector region extending from the buried collector region to a face of the semi... | 11/30/1999 |
| 5981341 | Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core A method for making a self-aligned isolated flash memory core without damaging tunnel oxide layers between memory element stacks and the silicon substrate supporting the stacks includes depositing three sidewall layers on the stacks, prior to etching isol... | 11/09/1999 |
| 5856228 | Manufacturing method for making bipolar device having double polysilicon structure A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor dev... | 01/05/1999 |
| 5843828 | Method for fabricating a semiconductor device with bipolar transistor A semiconductor device with a bipolar transistor that enables to realize a reliable, electric connection of an intrinsic base region with a base electrode is provided. A semiconductor substructure has a surface area. An intrinsic base region is formed in ... | 12/01/1998 |
| 5773349 | Method for making ultrahigh speed bipolar transistor An ultrahigh speed bipolar transistor has a base region which is formed from a P+ base polysilicon sidewall using a self-alignment method, and a base junction window which is formed in order to minimize the collector-base junction capacity. In ... | 06/30/1998 |
| 5721147 | Methods of forming bipolar junction transistors Methods of forming bipolar junction transistors include the steps of forming a first insulating layer on a face of a semiconductor substrate containing a collector region of first conductivity type therein and then forming an opening in the first insulati... | 02/24/1998 |
| 5654211 | Method for manufacturing ultra-high speed bipolar transistor A method of producing the bipolar transistor includes forming an aperture through a triple layer over an active region of an epitaxial layer, then forming a shallow polysilicon film at the bottom of the aperture. An intrinsic base region is formed by segr... | 08/05/1997 |
| 5641806 | Growth promotion and feed utilization in swine with Frenolicin B Methods and compositions for enhancing the growth and increasing the feed utilization of swine by using frenolicin B as the active ingredient to promote growth and increase feed utilization in swine. Frenolicin B is used in sufficient amounts to achieve t... | 06/24/1997 |
| 5569611 | Method of manufacturing a bipolar transistor operating at low temperature In a method of manufacturing a bipolar transistor, an oxide film pattern is formed on an epitaxial collector layer of a first conductive type which is formed on a buried layer of the first conductive type. A selectively-ion-implanted-collector (SIC) regio... | 10/29/1996 |
| 5541124 | Method for making bipolar transistor having double polysilicon structure A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor dev... | 07/30/1996 |
| 5508213 | Method of manufacturing a semiconductor device in which a semiconductor zone is formed through diffusion from a strip of polycrystalline silicon A method of manufacturing a semiconductor device whereby on a surface (3) of a semiconductor body (1) a conductor track (21) of polycrystalline silicon insulated from the surface (3) is provided in a layer of doped polycrystalline silicon (11) provided on... | 04/16/1996 |
| 5506157 | Method for fabricating pillar bipolar transistor Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterne... | 04/09/1996 |
| 5501992 | Method of manufacturing bipolar transistor having ring-shaped emitter and base A ring-shaped emitter region is formed either in a region a little toward an inner periphery or in a region a little toward an outer periphery in an upper layer portion of a ring-shaped base region of a bipolar transistor. A conductive layer is laminated ... | 03/26/1996 |
| 5484737 | Method for fabricating bipolar transistor Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region i... | 01/16/1996 |
| 5455185 | Method for manufacturing a bipolar transistor having base and collector in a vertical sequence In an epitaxial layer (3) deposited on a substrate (1), emitter (14), base (6) and collector (15) are disposed in a vertical sequence in such a way that the emitter (14) adjoins the surface of the epitaxial layer. Emitter (14) and base (6) are laterally b... | 10/03/1995 |
| 5391503 | Method of forming a stacked semiconductor device wherein semiconductor layers and insulating films are sequentially stacked and forming openings through such films and etchings using one of the insulating films as a mask According to this invention, a base extracting electrode is formed using a polysilicon side wall self-aligned with a base region so as to reduce a collector-base parasitic capacitance of a transistor. A base layer is formed on a semiconductor substrate by... | 02/21/1995 |
