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| Number | Title | Issue Date |
| 7935606 | Transistor manufacture A method in which an oxide layer is formed on material defining and surrounding an emitter window. The technique comprises depositing a non-conformal oxide layer on the surrounding material and in the emitter window, whereby the thickness of at least a portion of th... | 05/03/2011 |
| 7709339 | Method for producing a planar spacer, an associated bipolar transistor and an associated BiCMOS circuit arrangement Method for producing a planar spacer, an associated bipolar transistor and an associated BiCMOS circuit arrangement. The invention relates to a method for production of a planar spacer, of an associated bipolar transistor and of an associated BiCMOS circuit arrangem... | 05/04/2010 |
| 7615457 | Method of fabricating self-aligned bipolar transistor having tapered collector A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, th... | 11/10/2009 |
| 7611955 | Method of forming a bipolar transistor and semiconductor component thereof A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over t... | 11/03/2009 |
| 7397070 | Self-aligned transistor In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor. ... | 07/08/2008 |
| 7396723 | Method of manufacturing EEPROM device A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of ... | 07/08/2008 |
| 7338875 | Method of fabricating a semiconductor device having a toroidal-like junction Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is ... | 03/04/2008 |
| 7300850 | Method of forming a self-aligned transistor In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor. ... | 11/27/2007 |
| 7288829 | Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the... | 10/30/2007 |
| 7271051 | Methods of forming a plurality of capacitor devices The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conduc... | 09/18/2007 |
| 7268376 | Bipolar transistor for increasing signal transfer efficiency and method of manufacturing the same A bipolar transistor having a base semiconductor layer structure to minimize base parasitic resistance and a method of manufacturing the bipolar transistor are provided. In the provided bipolar transistor, a collector region of a second conductivity type, which is d... | 09/11/2007 |
| 7259050 | Semiconductor device and method of making the same A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of th... | 08/21/2007 |
| 7232732 | Semiconductor device with a toroidal-like junction Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is ... | 06/19/2007 |
| 7214978 | Semiconductor fabrication that includes surface tension control In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also includes vapor phase etching a layer adjacent to the side wall of the memory container with a vapor having a su... | 05/08/2007 |
| 7180157 | Bipolar transistor with a very narrow emitter feature A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped intrinsic emitter formed in the surface of the intrinsic base. A... | 02/20/2007 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe bas... | 02/06/2007 |
| 7169677 | Method for producing a spacer structure A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering depo... | 01/30/2007 |
| 7132368 | Method for repairing plasma damage after spacer formation for integrated circuit devices A method for processing integrated circuit memory devices. The method includes supporting a partially completed substrate, the substrate comprising a plurality of MOS gate structures. Each of the gate structures has substantially vertical regions that define sides o... | 11/07/2006 |
| 7119012 | Stabilization of Ni monosilicide thin films in CMOS devices using implantation of ions before silicidation A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the... | 10/10/2006 |
| 7118981 | Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component ... | 10/10/2006 |
| 7118935 | Bump style MEMS switch A microelectromechanical system switch may be formed with a protrusion defined on the substrate which makes contact with a deflectable member arranged over the substrate. The deflectable member may, for example, be a cantilevered arm or a deflectable beam. The protr... | 10/10/2006 |
| 7105415 | Method for the production of a bipolar transistor The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein and is bare towards the top. A monocrystalline base area is provided... | 09/12/2006 |
| 7095239 | Method for detecting defects that exhibit repetitive patterns A method for detecting defects in devices that are fabricated in repetitive patterns upon the surface of a substrate by the, repetitive utilization of masks and similar devices. A mask flaw will become manifest in a series of defective devices as the mask is success... | 08/22/2006 |
| 7094636 | Method of forming a conductive line A method of forming a conductive line includes forming conductive material received over a semiconductor substrate into a line having opposing sidewalls. Insulative material is deposited over the line, and is planarized. An insulating spacer forming layer is deposit... | 08/22/2006 |
| 7084028 | Semiconductor device and method of manufacturing a semiconductor device A semiconductor device comprises a semiconductor substrate having a cavity region inside; a first insulation film formed on the inner wall of the cavity region; a first electrode formed on the inner wall of the first insulation film in the cavity region, and having ... | 08/01/2006 |
| 7084051 | Manufacturing method for semiconductor substrate and manufacturing method for semiconductor device A purpose of the invention is to provide a manufacturing method for a semiconductor substrate in which a high quality strained silicon channel can easily be formed without sacrificing the processing efficiency of a wafer and to provide a manufacturing method for a s... | 08/01/2006 |
| 7060583 | Method for manufacturing a bipolar transistor having a polysilicon emitter In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an ins... | 06/13/2006 |
| 7041564 | Method for fabricating a self-aligned bipolar transistor According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transist... | 05/09/2006 |
| 7038298 | High fand fbipolar transistor and method of making same A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (112) that extends beyond the lower... | 05/02/2006 |
| 7026666 | Self-aligned NPN transistor with raised extrinsic base A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase i... | 04/11/2006 |
| 7015108 | Implanting carbon to form P-type drain extensions The use of a carbon implant, in addition to the conventional fluorine implant, may significantly reduce the transient enhanced diffusion in P-type source drain extension regions. As a result, resistivity may be reduced, and dopant density may be increased, increasin... | 03/21/2006 |
| 7005723 | Bipolar transistor and method of producing same In a method of producing a bipolar transistor, a semiconductor substrate having a substrate surface is provided. A base-terminal layer for providing a base terminal is formed on the substrate surface, and an emitter window having a wall area is formed in the base-te... | 02/28/2006 |
| 7005359 | Bipolar junction transistor with improved extrinsic base region and method of fabrication A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter... | 02/28/2006 |
| 6991991 | Method for preventing to form a spacer undercut in SEG pre-clean process A method for preventing to form a spacer undercut in SEG preclean process is provided. This present invention utilizes HFEG solution to etch the first spacer and the second spacer simultaneously, which can prevent from producing a spacer undercut, meanwhile; a nativ... | 01/31/2006 |
| 6972472 | Quasi self-aligned single polysilicon bipolar active device with intentional emitter window undercut An emitter stack for a quasi-self-aligned bipolar (NPN or PNP) transistor is formed where two layers over the emitter of a silicon substrate are windowed in a manner to under cut the top layer thereby exposing the substrate material. The emitter polysilicon structur... | 12/06/2005 |
| 6943077 | Selective spacer layer deposition method for forming spacers with different widths A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer... | 09/13/2005 |
| 6924216 | Semiconductor device having improved doping profiles and method of improving the doping profiles of a semiconductor device A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorph... | 08/02/2005 |
| 6924202 | Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer a... | 08/02/2005 |
| 6911368 | Arrangement for preventing short-circuiting in a bipolar double-poly transistor and a method of fabricating such an arrangement In a bipolar double-poly transistor comprising a layer of base silicon (1′) on a silicon substrate (2′), a first layer of silicon dioxide (3′) on the base silicon layer (1′), an emitter window (4′) extending through the f... | 06/28/2005 |
| 6905934 | Semiconductor device and a method of manufacturing the same The invention provides a bipolar transistor with improved performance. An insulation film comprising a silicon oxide film is formed by means of oxidation treatment on the side surface of an emitter aperture, and then an epitaxial layer comprised of SiGe is grown sel... | 06/14/2005 |
