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| Number | Title | Issue Date |
| 7892935 | Semiconductor process A semiconductor process is provided. The semiconductor process includes providing a substrate. Then, a surface treatment is performed to the substrate to form a buffer layer on the substrate. Next, a first pre-amorphous implantation is performed to the substrate. | 02/22/2011 |
| 7635634 | Dielectric apparatus and associated methods In an embodiment of the invention, an amorphous phase dielectric material is selectively formed over a substrate. The amorphous phase dielectric material is then converted into a crystalline phase dielectric material. ... | 12/22/2009 |
| 7585740 | Fully silicided extrinsic base transistor A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermin... | 09/08/2009 |
| 7541250 | Method for forming a self-aligned twin well region with simplified processing A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using ... | 06/02/2009 |
| 7479438 | Method to improve performance of a bipolar device using an amorphizing implant The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially t... | 01/20/2009 |
| 7425491 | Nanowire transistor with surrounding gate One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crys... | 09/16/2008 |
| 7364990 | Epitaxial crystal growth process in the manufacturing of a semiconductor device First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown,... | 04/29/2008 |
| 7343661 | Method for making condenser microphones A method for making condenser microphones includes: forming a fixed electrode layer structure of a plurality of fixed electrode units; forming a sacrificial layer of a plurality of sacrificial units on one side of the fixed electrode layer structure; forming a diaph... | 03/18/2008 |
| 7341920 | Method for forming a bipolar transistor device with self-aligned raised extrinsic base Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-art lithographi... | 03/11/2008 |
| 7294535 | Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A heat treatment is carried out for an amorphous semiconductor thin film, to thereby obtain a crystalline semiconductor thin fil... | 11/13/2007 |
| 7288827 | Self-aligned mask formed utilizing differential oxidation rates of materials A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe... | 10/30/2007 |
| 7247924 | Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysili... | 07/24/2007 |
| 7241649 | FinFET body contact structure A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface... | 07/10/2007 |
| 7232732 | Semiconductor device with a toroidal-like junction Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is ... | 06/19/2007 |
| 7217652 | Method of forming highly conductive semiconductor structures via plasma etch A process for making semiconductor structures uses a decoupled plasma source to produce a highly selective plasma etchant to form a structure with a thin adhesive layer and overlaying conductive layer. The preferred plasma is formed from chlorine and oxygen feed gas... | 05/15/2007 |
| 7206226 | Non-volatile memory element having memory gate and control gate adjacent to each other A memory element structured so as to reduce the size and improve reliability such that a memory gate and control gate are adjacent to each other. The side of a memory gate 115 in contact with a control gate 126 is formed by etching back. This side has ... | 04/17/2007 |
| 7193228 | EUV light source optical elements Apparatus and methods are disclosed for forming plasma generated EUV light source optical elements, e.g., reflectors comprising MLM stacks employing various binary layer materials and capping layer(s) including single and binary capping layers for utilization in pla... | 03/20/2007 |
| 7189625 | Micromachine and manufacturing method In a micromachine according to this invention, a polyimide film is formed on the surface of each electrode. The polyimide film is formed as follows. A substrate having each electrode and a counterelectrode are dipped in an electrodeposition polyimide solution, and a... | 03/13/2007 |
| 7170223 | Emitter with dielectric layer having implanted conducting centers An emitter has a dielectric layer formed on a conductor, with a thin metal layer over the dielectric. A plurality of conducting centers is in the dielectric layer to allow electrons to pass through the dielectric from the conductor to the thin metal layer via quantu... | 01/30/2007 |
| 7169677 | Method for producing a spacer structure A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering depo... | 01/30/2007 |
| 7161198 | Semiconductor integrated circuit device having MOS transistor An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a par... | 01/09/2007 |
| 7098113 | Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor... | 08/29/2006 |
| 7094699 | Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch... | 08/22/2006 |
| 7087979 | Bipolar transistor with an ultra small self-aligned polysilicon emitter The intrinsic base region of a bipolar transistor is formed to avoid a chemical interaction between the chemicals used in a chemical mechanical polishing step and the materials used to form the base region. The method includes the step of forming a trench in a layer... | 08/08/2006 |
| 7084016 | Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. An amorphous semiconductor thin film is irradiated with ultraviolet light or infrared light, to obtain a crystalline semiconduct... | 08/01/2006 |
| 7005359 | Bipolar junction transistor with improved extrinsic base region and method of fabrication A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter... | 02/28/2006 |
| 6974756 | Methods of forming shallow trench isolation A method of forming a shallow trench isolation is disclosed. An example method of forming a shallow trench isolation performs a planarization process for a substrate on which a hard mask and an insulation layer are formed, selectively etching the insulation layer on... | 12/13/2005 |
| 6965132 | Polycrystalline silicon emitter having an accurately controlled critical dimension According to a disclosed embodiment, an etch stop layer is fabricated on top of a base. An amorphous layer is then formed on top of the etch stop layer. An opening is then etched in the amorphous layer and the etch stop layer. The opening is etched with an opening w... | 11/15/2005 |
| 6960820 | Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrins... | 11/01/2005 |
| 6953741 | Methods of fabricating contacts for semiconductor devices utilizing a pre-flow process Methods for fabricating a contact of a semiconductor device are provided by patterning an interlayer dielectric of the semiconductor device to form a contact hole that exposes a silicon-based region of a first impurity type. The exposed silicon-based region is doped... | 10/11/2005 |
| 6951802 | Crystalline semiconductor film, method of manufacturing the same, and semiconductor device A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element soluti... | 10/04/2005 |
| 6936509 | STI pull-down to control SiGe facet growth A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation ... | 08/30/2005 |
| 6936871 | Heterojunction bipolar transistor with a base layer that contains bismuth A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III-V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a ... | 08/30/2005 |
| 6924216 | Semiconductor device having improved doping profiles and method of improving the doping profiles of a semiconductor device A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorph... | 08/02/2005 |
| 6919253 | Method of forming a semiconductor device including simultaneously forming a single crystalline epitaxial layer and a polycrystalline or amorphous layer A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously ... | 07/19/2005 |
| 6913981 | Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielect... | 07/05/2005 |
| 6910637 | Stacked small memory card A stacked small memory card includes an upper memory card and a lower memory card, the upper memory card and the lower memory card respectively formed a first heat sink and a second heat sink, the first heat sink and the second heat sink are stacked together, so tha... | 06/28/2005 |
| 6905934 | Semiconductor device and a method of manufacturing the same The invention provides a bipolar transistor with improved performance. An insulation film comprising a silicon oxide film is formed by means of oxidation treatment on the side surface of an emitter aperture, and then an epitaxial layer comprised of SiGe is grown sel... | 06/14/2005 |
| 6900519 | Diffused extrinsic base and method for fabrication The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced ... | 05/31/2005 |
| 6887765 | Method for manufacturing a bipolar junction transistor According to one embodiment of the invention, a method used in manufacturing an intermediate structure in a bipolar junction transistor includes implanting a base dopant in a semiconductor substrate to form a base, forming a dielectric layer outwardly from the semic... | 05/03/2005 |
