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| Number | Title | Issue Date |
| 7838378 | Semiconductor device and manufacturing method thereof A semiconductor device and a method for manufacturing the semiconductor device are provided. The method includes forming a collector region of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a base region of the first co... | 11/23/2010 |
| 7642168 | System and method for providing a self aligned bipolar transistor using a sacrificial polysilicon external base A system and method are disclosed for providing a self aligned bipolar transistor using a sacrificial polysilicon external base. An active region of a transistor is formed and a sacrificial polysilicon external base is formed above the active region of the transisto... | 01/05/2010 |
| 7435659 | Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implan... | 10/14/2008 |
| 7341920 | Method for forming a bipolar transistor device with self-aligned raised extrinsic base Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-art lithographi... | 03/11/2008 |
| 7338875 | Method of fabricating a semiconductor device having a toroidal-like junction Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is ... | 03/04/2008 |
| 7304334 | Silicon carbide bipolar junction transistors having epitaxial base regions and multilayer emitters and methods of fabricating the same Bipolar junction transistors (BJTs) are provided including silicon carbide (SiC) substrates. An epitaxial SiC base region is provided on the SiC substrate. The epitaxial SiC base region has a first conductivity type. An epitaxial SiC emitter region is also provided ... | 12/04/2007 |
| 7285470 | Method for the production of a bipolar semiconductor component, especially a bipolar transistor, and corresponding bipolar semiconductor component The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component. The inventive method comprises the following steps: a first semiconductor area (32, 34) of a... | 10/23/2007 |
| 7285830 | Lateral bipolar junction transistor in CMOS flow An improved lateral bipolar junction transistor and a method of forming such a lateral bipolar transistor without added mask in CMOS flow on a p-substrate are disclosed. The CMOS flow includes patterning and n-well implants; pattern and implant pocket implants for c... | 10/23/2007 |
| 7282418 | Method for fabricating a self-aligned bipolar transistor without spacers According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated o... | 10/16/2007 |
| 7273789 | Method of fabricating heterojunction bipolar transistor Provided is a method of fabricating a heterojunction bipolar transistor (HBT). The method includes: sequentially depositing a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter capping layer on a substrate; forming an emitter elec... | 09/25/2007 |
| 7271070 | Method for producing transistors The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is de... | 09/18/2007 |
| 7268412 | Double polysilicon bipolar transistor A bipolar transistor with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and s... | 09/11/2007 |
| 7268376 | Bipolar transistor for increasing signal transfer efficiency and method of manufacturing the same A bipolar transistor having a base semiconductor layer structure to minimize base parasitic resistance and a method of manufacturing the bipolar transistor are provided. In the provided bipolar transistor, a collector region of a second conductivity type, which is d... | 09/11/2007 |
| 7268413 | Bipolar transistors with low-resistance emitter contacts Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching spe... | 09/11/2007 |
| 7265010 | High performance vertical PNP transistor method The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, an... | 09/04/2007 |
| 7247892 | Imaging array utilizing thyristor-based pixel elements An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-ty... | 07/24/2007 |
| 7241699 | Wide bandgap semiconductor device construction The invention includes methods for precisely and accurately etching layers of wide bandgap semiconductor material. According to one aspect of the invention, the method includes providing a multi-layer laminate including at least a first and second layer of wide band... | 07/10/2007 |
| 7157345 | Source side injection storage device and method therefor A memory charge storage device has regions of sacrificial material overlying a substrate (12). For each memory cell a first doped region (20) and a second doped region (24) are formed within the substrate and on opposite sides of one (16)... | 01/02/2007 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
| 7141478 | Multi-stage EPI process for forming semiconductor devices, and resulting device The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting ... | 11/28/2006 |
| 7132715 | Semiconductor device having a spacer layer doped with slower diffusing atoms than substrate A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient o... | 11/07/2006 |
| 7132701 | Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same con... | 11/07/2006 |
| 7095006 | Photodetector with hetero-structure using lateral growth A structure and method of fabrication for a Si based material p-i-n photodetector is disclosed. The light is absorbed in an undoped layer containing SiGe or Ge in such a manner that the absorption length is not limited by a critical thickness of the SiGe or Ge layer... | 08/22/2006 |
| 7067383 | Method of making bipolar transistors and resulting product A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a ... | 06/27/2006 |
| 7060585 | Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization A method utilizing in-place bonding and amorphization/templated recrystallization (ATR) is provided for making bulk and semiconductor-on-insulator substrates having coplanar semiconductor layers of different crystallographic orientations. First and second semiconduc... | 06/13/2006 |
| 7042689 | High voltage tolerant ESD design for analog and RF applications in deep submicron CMOS technologies The invention describes structures and a process for providing ESD semiconductor protection with reduced input capacitance that has special advantages for high frequency analog pin I/O applications. The structures consist of a first and second NMOS serial pair whose... | 05/09/2006 |
| 7038298 | High fand fbipolar transistor and method of making same A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (112) that extends beyond the lower... | 05/02/2006 |
| 7034398 | Semiconductor device having contact plug and buried conductive film therein A semiconductor device includes an active element structure that is formed on a semiconductor substrate and has a connection region formed in the surface of the semiconductor substrate. A contact hole extends from a surface of a first insulating film formed on the s... | 04/25/2006 |
| 7026666 | Self-aligned NPN transistor with raised extrinsic base A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase i... | 04/11/2006 |
| 7012009 | Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process A method for making an improved silicon-germanium layer on a substrate for the base of a heterojunction bipolar transistor is achieved using a two-temperature process. The method involves growing a seed layer at a higher temperature to reduce the grain size with sho... | 03/14/2006 |
| 6992338 | CMOS transistor spacers formed in a BiCMOS process According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited ... | 01/31/2006 |
| 6979626 | Method for fabricating a self-aligned bipolar transistor having increased manufacturability and related structure According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated o... | 12/27/2005 |
| 6969671 | Semiconductor integrated device and method of fabrication thereof A diffusion layer 3a of a silicon substrate, a polycrystalline silicon material 10, or a gate electrode 12 is connected to a conductive film 8 through a titanium silicide film 6 within a contact hole 5 provided in an ... | 11/29/2005 |
| 6960820 | Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrins... | 11/01/2005 |
| 6939768 | Method of forming self-aligned contacts A method of forming self-aligned contacts that includes providing at least one stacked-gate structure on a semiconductor substrate, forming a first dielectric layer on the stacked-gate structure and the semiconductor substrate, forming a second dielectric layer on t... | 09/06/2005 |
| 6939761 | Methods of forming buried bit line DRAM circuitry A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Con... | 09/06/2005 |
| 6936519 | Double polysilicon bipolar transistor and method of manufacture therefor A bipolar transistor, and manufacturing method therefor, with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and ov... | 08/30/2005 |
| 6933202 | Method for integrating SiGe NPN and vertical PNP devices on a substrate and related structure According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulat... | 08/23/2005 |
| 6924202 | Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer a... | 08/02/2005 |
| 6919615 | Semiconductor device for integrated injection logic cell and process for fabricating the same A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised o... | 07/19/2005 |
