Class 438/363 - With epitaxial semiconductor layer formation

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a bipolar transistor utilizing in addition
No. of patents: 155
Last issue date: 03/22/2011

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Number	Title	Issue Date
7910449	Semiconductor device and method of manufacturing the same In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands....	03/22/2011
7378324	Selective links in silicon hetero-junction bipolar transistors using carbon doping and method of forming same Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; ...	05/27/2008
7279399	Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o...	10/09/2007
7265434	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o...	09/04/2007
7226835	Versatile system for optimizing current gain in bipolar transistor structures Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406	06/05/2007
7223668	Method of etching metallic thin film on thin film resistor An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and ope...	05/29/2007
7211863	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o...	05/01/2007
7202536	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o...	04/10/2007
7180923	Laser employing a zinc-doped tunnel-junction An improved tunnel junction structure and a VCSEL that uses this structure is disclosed. The tunnel junction includes first, second, and third layers that include materials of the InP family of materials. The first layer is doped with n-type dopant species to a conc...	02/20/2007
7164186	Structure of semiconductor device with sinker contact region A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the burie...	01/16/2007
7135738	Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o...	11/14/2006
7132321	Vertical conducting power semiconductor devices implemented by deep etch Semiconductor substrates suitable for making thin vertical current conducting devices are made by providing a relatively thick semiconducting substrate with at least one conductivity type having a thickness of from about 100 μm to 700 μm. At least one active devic...	11/07/2006
7091100	Polysilicon bipolar transistor and method of manufacturing it In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor substrate, a poly-crystal base terminal layer is produced on the etch stop layer and an emitter window is etched ...	08/15/2006
7060550	Method of fabricating a bipolar junction transistor A method for fabricating a bipolar junction transistor on a wafer is disclosed. The wafer has a N-type doped area and a plurality of isolated structures. A protection layer is formed on the wafer and portions of the protection layer are then removed to expose portio...	06/13/2006
7033895	Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is fo...	04/25/2006
7008839	Method for manufacturing semiconductor thin film A substrate with a second semiconductor layer and a second mask film formed thereon is subjected to a heat treatment in an oxidizing atmosphere. Thus, second oxidized regions are formed through oxidization of the second semiconductor layer in regions of the second s...	03/07/2006
6995068	Double-implant high performance varactor and method for manufacturing same A varactor designed to enable voltage controlled oscillator (VCO) integration in wireless systems is the base-emitter junction of a specially optimized NPN device formed with a double base implant. A first, shallow implant optimizes capacitance, leakage current, and...	02/07/2006
6927118	Method of fabricating a bipolar transistor utilizing a dry etching and a wet etching to define a base junction opening The present invention discloses a process of fabricating a semiconductor device comprising the steps of: forming a collector layer of a first conductivity type at a portion of a surface of a semiconductor substrate; forming a collector opening portion in a first ins...	08/09/2005
6914308	Vertical PNP bipolar transistor A semiconductor device in which a vertical pnp-bipolar transistor is formed in a prescribed element region on a semiconductor substrate includes: a buried n+-layer of a high concentration formed in the prescribed element region; and a p-type collector lay...	07/05/2005
6881641	Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so t...	04/19/2005
6767798	Method of forming self-aligned NPN transistor with raised extrinsic base A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase i...	07/27/2004
6699760	Method for growing layers of group III-nitride semiconductor having electrically passivated threading defects One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconducto...	03/02/2004
6624045	Thermal conducting trench in a seminconductor structure and method for forming the same The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a co...	09/23/2003
6593200	Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation A method of forming a semiconductor device with an inductor and/or high speed interconnect. The method comprises forming an epitaxial layer over the substrate, forming an opening through the epitaxial layer to expose an underlying region of the substrate,...	07/15/2003
6579774	Semiconductor device fabrication method A semiconductor device fabrication method includes the steps of forming a first insulation layer and a first semiconductor layer sequentially on a semiconductor substrate having a buried diffusion region therein. A second insulation layer is formed on the...	06/17/2003
6503773	Low threading dislocation density relaxed mismatched epilayers without high temperature growth A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited o...	01/07/2003
6444591	Method for reducing contamination prior to epitaxial growth and related structure According to a disclosed embodiment, the surface of a semiconductor wafer is covered by an etch stop layer. For example, the etch stop layer can be composed of silicon dioxide. A cap layer is then fabricated over the etch stop layer. For example, the cap ...	09/03/2002
6436780	Semiconductor device A number of npn and pnp bipolar transistors are formed in a single chip of silicon, so that some of the transistors have a greater frequency response than others The higher frequency transistors have their emitters located closer to the collectors, by pos...	08/20/2002
6331470	Process for manufacturing a semiconductor material wafer having power regions dielectrically insulated from circuitry regions A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and th...	12/18/2001
6313000	Process for formation of vertically isolated bipolar transistor device A vertically-isolated bipolar transistor occupying reduced surface area is fabricated by circumscribing an expected active device region within a first narrow trench. The first trench is filled with sacrificial material impermeable to diffusion of conduct...	11/06/2001
6297118	Vertical bipolar semiconductor power transistor with an interdigitzed geometry, with optimization of the base-to-emitter potential difference A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buri...	10/02/2001
6242313	Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of polysilicon field plates...	06/05/2001
6228733	Non-selective epitaxial depostion technology Base layer formation without the use of selective epitaxial deposition is described. The process begins with the deposition of a seed layer of polysilicon over both the field oxide and the wafer surface that lies between them. An opening in said seed laye...	05/08/2001
6171894	Method of manufacturing BICMOS integrated circuits on a conventional CMOS substrate A method of manufacturing a BICMOS integrated circuit including an NPN transistor in a heavily-doped P-type wafer coated with a lightly-doped P-type layer, including the steps of forming an N well of collector of a bipolar transistor; coating the structur...	01/09/2001
6140196	Method of fabricating high power bipolar junction transistor A method of fabricating a high power bipolar junction transistor. A P-type substrate having an N-type buried region is provided and a trench is formed within the substrate to expose the buried region. N-type ions are implanted and driven into the sidewall...	10/31/2000
6057184	Semiconductor device fabrication method using connecting implants A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecti...	05/02/2000
6020246	Forming a self-aligned epitaxial base bipolar transistor An improved method and an apparatus for forming a self-aligned epitaxial base bipolar transistor in a semiconductor material is disclosed. The method of the invention involves forming an intrinsic base region formed by growing an epitaxial semiconductor m...	02/01/2000
6015726	Semiconductor device and method of producing the same A method of producing a semiconductor device having a bipolar transistor and a CMOS (Complementary Metal Oxide Semiconductor) transistor is disclosed. An epitaxial layer is formed on a semiconductor substrate having an n-type buried layer and a p-type bur...	01/18/2000
6010937	Reduction of dislocations in a heteroepitaxial semiconductor structure A heteroepitaxial semiconductor device having reduced density of threading dislocations and a process for forming such a device. According to one embodiment, the device includes a substrate which is heat treated to a temperature in excess of 1000° C., a ...	01/04/2000
5909623	Manufacturing method of semiconductor device A manufacturing method of the present invention comprises the first step of forming an epitaxial base layer in an opening of an element-isolating oxide film on a semiconductor substrate in a non-selection condition, the second step of growing a silicon ox...	06/01/1999

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Class 438/363 - With epitaxial semiconductor layer formation